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ARM: dts: Add support for DRA72x family of devices
DRA722 is part of DRA72x family which are single core cortex A15 devices with most infrastructure IPs otherwise same as whats on the DRA74x family. So move the cpu nodes into dra74x.dtsi and dra72x.dtsi respectively. Also add a minimal dra72-evm dts file. Signed-off-by: Rajendra Nayak <rnayak@ti.com> Cc: linux-doc@vger.kernel.org Cc: devicetree@vger.kernel.org Acked-by: Arnd Bergmann <arnd@arndb.de> [tony@atomide.com: updated for Makefile sorting] Signed-off-by: Tony Lindgren <tony@atomide.com>
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@ -80,7 +80,10 @@ SoCs:
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compatible = "ti,omap5432", "ti,omap5"
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- DRA742
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compatible = "ti,dra7xx", "ti,dra7"
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compatible = "ti,dra742", "ti,dra74", "ti,dra7"
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- DRA722
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compatible = "ti,dra722", "ti,dra72", "ti,dra7"
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- AM4372
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compatible = "ti,am4372", "ti,am43"
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@ -120,5 +123,8 @@ Boards:
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- AM437x GP EVM
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compatible = "ti,am437x-gp-evm", "ti,am4372", "ti,am43"
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- DRA7 EVM: Software Developement Board for DRA7XX
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compatible = "ti,dra7-evm", "ti,dra7"
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- DRA742 EVM: Software Developement Board for DRA742
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compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7"
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- DRA722 EVM: Software Development Board for DRA722
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compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7"
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@ -290,7 +290,8 @@ dtb-$(CONFIG_SOC_AM43XX) += am43x-epos-evm.dtb \
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dtb-$(CONFIG_SOC_OMAP5) += omap5-cm-t54.dtb \
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omap5-sbc-t54.dtb \
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omap5-uevm.dtb
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dtb-$(CONFIG_SOC_DRA7XX) += dra7-evm.dtb
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dtb-$(CONFIG_SOC_DRA7XX) += dra7-evm.dtb \
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dra72-evm.dtb
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dtb-$(CONFIG_ARCH_ORION5X) += orion5x-lacie-ethernet-disk-mini-v2.dtb
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dtb-$(CONFIG_ARCH_PRIMA2) += prima2-evb.dtb
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dtb-$(CONFIG_ARCH_QCOM) += qcom-msm8660-surf.dtb \
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@ -7,11 +7,11 @@
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*/
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/dts-v1/;
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#include "dra7.dtsi"
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#include "dra74x.dtsi"
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/ {
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model = "TI DRA7";
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compatible = "ti,dra7-evm", "ti,dra7";
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model = "TI DRA742";
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compatible = "ti,dra7-evm", "ti,dra742", "ti,dra74", "ti,dra7";
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memory {
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device_type = "memory";
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@ -33,33 +33,6 @@
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serial5 = &uart6;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0>;
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operating-points = <
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/* kHz uV */
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1000000 1060000
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1176000 1160000
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>;
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clocks = <&dpll_mpu_ck>;
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clock-names = "cpu";
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clock-latency = <300000>; /* From omap-cpufreq driver */
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <1>;
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};
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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24
arch/arm/boot/dts/dra72-evm.dts
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24
arch/arm/boot/dts/dra72-evm.dts
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@ -0,0 +1,24 @@
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/*
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* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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/dts-v1/;
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#include "dra72x.dtsi"
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/ {
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model = "TI DRA722";
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compatible = "ti,dra72-evm", "ti,dra722", "ti,dra72", "ti,dra7";
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memory {
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device_type = "memory";
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reg = <0x80000000 0x40000000>; /* 1024 MB */
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};
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};
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&uart1 {
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status = "okay";
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};
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25
arch/arm/boot/dts/dra72x.dtsi
Normal file
25
arch/arm/boot/dts/dra72x.dtsi
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@ -0,0 +1,25 @@
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/*
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* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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* Based on "omap4.dtsi"
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*/
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#include "dra7.dtsi"
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/ {
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compatible = "ti,dra722", "ti,dra72", "ti,dra7";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0>;
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};
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};
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};
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41
arch/arm/boot/dts/dra74x.dtsi
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41
arch/arm/boot/dts/dra74x.dtsi
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@ -0,0 +1,41 @@
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/*
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* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com/
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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* Based on "omap4.dtsi"
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*/
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#include "dra7.dtsi"
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/ {
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compatible = "ti,dra742", "ti,dra74", "ti,dra7";
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <0>;
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operating-points = <
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/* kHz uV */
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1000000 1060000
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1176000 1160000
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>;
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clocks = <&dpll_mpu_ck>;
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clock-names = "cpu";
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clock-latency = <300000>; /* From omap-cpufreq driver */
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};
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cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a15";
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reg = <1>;
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};
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};
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};
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