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dt-bindings: clock: Add YAML schemas for LPASS clocks on SC7180
The LPASS(Low Power Audio Subsystem) clock provider have a bunch of generic properties that are needed in a device tree. Also add clock ids for GCC LPASS and LPASS Core clock IDs for LPASS client to request for the clocks. Signed-off-by: Taniya Das <tdas@codeaurora.org> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/1595606878-2664-3-git-send-email-tdas@codeaurora.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/qcom,sc7180-lpasscorecc.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm LPASS Core Clock Controller Binding for SC7180
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maintainers:
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- Taniya Das <tdas@codeaurora.org>
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description: |
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Qualcomm LPASS core clock control module which supports the clocks and
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power domains on SC7180.
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See also:
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- dt-bindings/clock/qcom,lpasscorecc-sc7180.h
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properties:
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compatible:
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enum:
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- qcom,sc7180-lpasshm
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- qcom,sc7180-lpasscorecc
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clocks:
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items:
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- description: gcc_lpass_sway clock from GCC
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clock-names:
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items:
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- const: iface
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power-domains:
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maxItems: 1
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'#clock-cells':
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const: 1
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'#power-domain-cells':
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const: 1
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reg:
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minItems: 1
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items:
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- description: lpass core cc register
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- description: lpass audio cc register
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reg-names:
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items:
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- const: lpass_core_cc
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- const: lpass_audio_cc
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if:
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properties:
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compatible:
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contains:
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const: qcom,sc7180-lpasshm
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then:
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properties:
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reg:
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maxItems: 1
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else:
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properties:
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reg:
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minItems: 2
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required:
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- compatible
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- reg
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- clocks
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- clock-names
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- '#clock-cells'
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- '#power-domain-cells'
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/clock/qcom,gcc-sc7180.h>
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#include <dt-bindings/clock/qcom,lpasscorecc-sc7180.h>
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clock-controller@63000000 {
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compatible = "qcom,sc7180-lpasshm";
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reg = <0x63000000 0x28>;
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clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>;
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clock-names = "iface";
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#clock-cells = <1>;
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#power-domain-cells = <1>;
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};
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- |
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clock-controller@62d00000 {
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compatible = "qcom,sc7180-lpasscorecc";
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reg = <0x62d00000 0x50000>, <0x62780000 0x30000>;
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reg-names = "lpass_core_cc", "lpass_audio_cc";
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clocks = <&gcc GCC_LPASS_CFG_NOC_SWAY_CLK>;
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clock-names = "iface";
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power-domains = <&lpass_hm LPASS_CORE_HM_GDSCR>;
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#clock-cells = <1>;
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#power-domain-cells = <1>;
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};
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...
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#define GCC_MSS_Q6_MEMNOC_AXI_CLK 128
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#define GCC_MSS_SNOC_AXI_CLK 129
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#define GCC_SEC_CTRL_CLK_SRC 130
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#define GCC_LPASS_CFG_NOC_SWAY_CLK 131
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/* GCC resets */
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#define GCC_QUSB2PHY_PRIM_BCR 0
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29
include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h
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29
include/dt-bindings/clock/qcom,lpasscorecc-sc7180.h
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/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_LPASS_CORE_CC_SC7180_H
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#define _DT_BINDINGS_CLK_QCOM_LPASS_CORE_CC_SC7180_H
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/* LPASS_CORE_CC clocks */
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#define LPASS_LPAAUDIO_DIG_PLL 0
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#define LPASS_LPAAUDIO_DIG_PLL_OUT_ODD 1
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#define CORE_CLK_SRC 2
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#define EXT_MCLK0_CLK_SRC 3
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#define LPAIF_PRI_CLK_SRC 4
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#define LPAIF_SEC_CLK_SRC 5
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#define LPASS_AUDIO_CORE_CORE_CLK 6
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#define LPASS_AUDIO_CORE_EXT_MCLK0_CLK 7
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#define LPASS_AUDIO_CORE_LPAIF_PRI_IBIT_CLK 8
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#define LPASS_AUDIO_CORE_LPAIF_SEC_IBIT_CLK 9
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#define LPASS_AUDIO_CORE_SYSNOC_MPORT_CORE_CLK 10
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/* LPASS Core power domains */
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#define LPASS_CORE_HM_GDSCR 0
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/* LPASS Audio power domains */
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#define LPASS_AUDIO_HM_GDSCR 0
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#define LPASS_PDC_HM_GDSCR 1
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#endif
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