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ASoC: Fix WM8996 24.576MHz clock operation

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Record the clock after the divider as that is what all SYSCLK users see.
Without this the other clock configuration in the device comes out at
half rate.

Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: stable@kernel.org
This commit is contained in:
Mark Brown 2011-12-10 20:38:32 +08:00
parent 974edd30be
commit 37d5993c5c
1 changed files with 1 additions and 0 deletions
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1
sound/soc/codecs/wm8996.c
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@ -1968,6 +1968,7 @@ static int wm8996_set_sysclk(struct snd_soc_dai *dai,
break;
case 24576000:
ratediv = WM8996_SYSCLK_DIV;
wm8996->sysclk /= 2;
case 12288000:
snd_soc_update_bits(codec, WM8996_AIF_RATE,
WM8996_SYSCLK_RATE, WM8996_SYSCLK_RATE);