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net: ipa: support different event ring encoding

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Starting with IPA v5.0, a channel's event ring index is encoded in
a field in the CH_C_CNTXT_1 GSI register rather than CH_C_CNTXT_0.
Define a new field ID for the former register and encode the event
ring in the appropriate register.

Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
This commit is contained in:
Alex Elder 2023-02-15 13:53:51 -06:00 committed by Paolo Abeni
parent 62747512eb
commit 37cd29ec84
2 changed files with 6 additions and 2 deletions
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5
drivers/net/ipa/gsi.c
View File

@ -840,12 +840,15 @@ static void gsi_channel_program(struct gsi_channel *channel, bool doorbell)
val = ch_c_cntxt_0_type_encode(gsi->version, reg, GSI_CHANNEL_TYPE_GPI);
if (channel->toward_ipa)
val |= reg_bit(reg, CHTYPE_DIR);
val |= reg_encode(reg, ERINDEX, channel->evt_ring_id);
if (gsi->version < IPA_VERSION_5_0)
val |= reg_encode(reg, ERINDEX, channel->evt_ring_id);
val |= reg_encode(reg, ELEMENT_SIZE, GSI_RING_ELEMENT_SIZE);
iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id));
reg = gsi_reg(gsi, CH_C_CNTXT_1);
val = reg_encode(reg, CH_R_LENGTH, size);
if (gsi->version >= IPA_VERSION_5_0)
val |= reg_encode(reg, CH_ERINDEX, channel->evt_ring_id);
iowrite32(val, gsi->virt + reg_n_offset(reg, channel_id));
/* The context 2 and 3 registers store the low-order and

3
drivers/net/ipa/gsi_reg.h
View File

@ -102,7 +102,7 @@ enum gsi_reg_ch_c_cntxt_0_field_id {
CH_EE,
CHID,
CHTYPE_PROTOCOL_MSB, /* IPA v4.5-4.11 */
ERINDEX,
ERINDEX, /* Not IPA v5.0+ */
CHSTATE,
ELEMENT_SIZE,
};
@ -124,6 +124,7 @@ enum gsi_channel_type {
/* CH_C_CNTXT_1 register */
enum gsi_reg_ch_c_cntxt_1_field_id {
CH_R_LENGTH,
CH_ERINDEX, /* IPA v5.0+ */
};
/* CH_C_QOS register */