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drm/nvc0-/gr: shift wrapping bug in nvc0_grctx_generate_r406800

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We care about the upper 32 bits here so we have to use 1ULL instead of 1
to avoid a shift wrapping bug.

Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Maarten Lankhorst <maarten.lankhorst@canonical.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
This commit is contained in:
Dan Carpenter 2013-11-12 13:34:11 +01:00 committed by Ben Skeggs
parent 35c336707f
commit 377cfdc6ee
1 changed files with 1 additions and 1 deletions
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2
drivers/gpu/drm/nouveau/core/engine/graph/ctxnvc0.c
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@ -1039,7 +1039,7 @@ nvc0_grctx_generate_r406800(struct nvc0_graph_priv *priv)
} while (!tpcnr[gpc]);
tpc = priv->tpc_nr[gpc] - tpcnr[gpc]--;
tpc_set |= 1 << ((gpc * 8) + tpc);
tpc_set |= 1ULL << ((gpc * 8) + tpc);
}
nv_wr32(priv, 0x406800 + (i * 0x20), lower_32_bits(tpc_set));