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drm/i915/icl: Define TRANS_CONF register for DSI

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This patch defines TRANS_CONF registers for DSI ports
0 and 1. Bitfields of these registers used for enabling
and reading the current state of transcoder.

v2: Add blank line before comment

v3 by Jani:
 - Move DSI specific .pipe_offsets to GEN11_FEATURES
 - Macro placement and comment juggling

Signed-off-by: Madhav Chauhan <madhav.chauhan@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/3aa11e41ea0d4eb434423cc5ddf0a63b19d54deb.1539613303.git.jani.nikula@intel.com
This commit is contained in:
Madhav Chauhan 2018-10-15 17:28:04 +03:00 committed by Jani Nikula
parent d1aeb5f399
commit 372610f3c8
2 changed files with 11 additions and 0 deletions
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3
drivers/gpu/drm/i915/i915_pci.c
View File

@ -595,6 +595,9 @@ static const struct intel_device_info intel_cannonlake_info = {
#define GEN11_FEATURES \
GEN10_FEATURES, \
.pipe_offsets = { PIPE_A_OFFSET, PIPE_B_OFFSET, \
PIPE_C_OFFSET, PIPE_EDP_OFFSET, \
PIPE_DSI0_OFFSET, PIPE_DSI1_OFFSET }, \
.trans_offsets = { TRANSCODER_A_OFFSET, TRANSCODER_B_OFFSET, \
TRANSCODER_C_OFFSET, TRANSCODER_EDP_OFFSET, \
TRANSCODER_DSI0_OFFSET, TRANSCODER_DSI1_OFFSET}, \

8
drivers/gpu/drm/i915/i915_reg.h
View File

@ -5614,6 +5614,10 @@ enum {
*/
#define PIPE_EDP_OFFSET 0x7f000
/* ICL DSI 0 and 1 */
#define PIPE_DSI0_OFFSET 0x7b000
#define PIPE_DSI1_OFFSET 0x7b800
#define _MMIO_PIPE2(pipe, reg) _MMIO(dev_priv->info.pipe_offsets[pipe] - \
dev_priv->info.pipe_offsets[PIPE_A] + (reg) + \
dev_priv->info.display_mmio_offset)
@ -6202,6 +6206,10 @@ enum {
#define _DSPBOFFSET (dev_priv->info.display_mmio_offset + 0x711A4)
#define _DSPBSURFLIVE (dev_priv->info.display_mmio_offset + 0x711AC)
/* ICL DSI 0 and 1 */
#define _PIPEDSI0CONF 0x7b008
#define _PIPEDSI1CONF 0x7b808
/* Sprite A control */
#define _DVSACNTR 0x72180
#define DVS_ENABLE (1 << 31)