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arm64: cpuinfo: remove I-cache VIPT aliasing detection
The CCSIDR_EL1.{NumSets,Associativity,LineSize} fields are only for use in conjunction with set/way cache maintenance and are not guaranteed to represent the actual microarchitectural features of a design. The architecture explicitly states: | You cannot make any inference about the actual sizes of caches based | on these parameters. We currently use these fields to determine whether or the I-cache is aliasing, which is bogus and known to break on some platforms. Instead, assume the I-cache is always aliasing if it advertises a VIPT policy. Acked-by: Mark Rutland <mark.rutland@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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@ -63,19 +63,6 @@ extern unsigned long __icache_flags;
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#define CACHE_NUMSETS(x) (CCSIDR_EL1_NUMSETS(x) + 1)
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#define CACHE_ASSOCIATIVITY(x) (CCSIDR_EL1_ASSOCIATIVITY(x) + 1)
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extern u64 __attribute_const__ cache_get_ccsidr(u64 csselr);
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/* Helpers for Level 1 Instruction cache csselr = 1L */
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static inline int icache_get_linesize(void)
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{
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return CACHE_LINESIZE(cache_get_ccsidr(1L));
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}
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static inline int icache_get_numsets(void)
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{
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return CACHE_NUMSETS(cache_get_ccsidr(1L));
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}
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/*
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* Whilst the D-side always behaves as PIPT on AArch64, aliasing is
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* permitted in the I-cache.
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@ -289,20 +289,17 @@ static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info)
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unsigned int cpu = smp_processor_id();
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u32 l1ip = CTR_L1IP(info->reg_ctr);
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if (l1ip != ICACHE_POLICY_PIPT) {
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/*
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* VIPT caches are non-aliasing if the VA always equals the PA
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* in all bit positions that are covered by the index. This is
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* the case if the size of a way (# of sets * line size) does
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* not exceed PAGE_SIZE.
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*/
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u32 waysize = icache_get_numsets() * icache_get_linesize();
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if (l1ip != ICACHE_POLICY_VIPT || waysize > PAGE_SIZE)
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set_bit(ICACHEF_ALIASING, &__icache_flags);
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}
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if (l1ip == ICACHE_POLICY_AIVIVT)
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switch (l1ip) {
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case ICACHE_POLICY_PIPT:
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break;
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default:
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case ICACHE_POLICY_AIVIVT:
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set_bit(ICACHEF_AIVIVT, &__icache_flags);
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/* Fallthrough */
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case ICACHE_POLICY_VIPT:
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/* Assume aliasing */
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set_bit(ICACHEF_ALIASING, &__icache_flags);
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}
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pr_info("Detected %s I-cache on CPU%d\n", icache_policy_str[l1ip], cpu);
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}
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