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pinctrl: renesas: r8a779g0: Add missing MODSELx for AVBx

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AVB1 needs MODSEL6, AVB2 needs MODSEL5 settings.
This patch adds missing MODSELx settings for the affected pins.

Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Link: https://lore.kernel.org/r/87k08xsj81.wl-kuninori.morimoto.gx@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Kuninori Morimoto 2022-07-01 01:41:02 +00:00 committed by Geert Uytterhoeven
parent 36fb7b8af5
commit 36611d28f5
1 changed files with 30 additions and 28 deletions
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58
drivers/pinctrl/renesas/pfc-r8a779g0.c
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@ -715,27 +715,29 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_NOGM(0, TSN0_AVTP_PPS1, SEL_TSN0_AVTP_PPS1_1),
PINMUX_IPSR_NOGM(0, TSN0_MDC, SEL_TSN0_MDC_1),
/* TSN0 without MODSEL5 */
PINMUX_SINGLE(AVB2_RX_CTL),
PINMUX_SINGLE(AVB2_TX_CTL),
PINMUX_SINGLE(AVB2_RXC),
PINMUX_SINGLE(AVB2_RD0),
PINMUX_SINGLE(AVB2_TXC),
PINMUX_SINGLE(AVB2_TD0),
PINMUX_SINGLE(AVB2_RD1),
PINMUX_SINGLE(AVB2_RD2),
PINMUX_SINGLE(AVB2_TD1),
PINMUX_SINGLE(AVB2_TD2),
PINMUX_SINGLE(AVB2_MDIO),
PINMUX_SINGLE(AVB2_RD3),
PINMUX_SINGLE(AVB2_TD3),
PINMUX_SINGLE(AVB2_TXCREFCLK),
PINMUX_SINGLE(AVB2_MDC),
PINMUX_SINGLE(AVB2_MAGIC),
PINMUX_SINGLE(AVB2_PHY_INT),
PINMUX_SINGLE(AVB2_LINK),
PINMUX_SINGLE(AVB2_AVTP_MATCH),
PINMUX_SINGLE(AVB2_AVTP_CAPTURE),
PINMUX_SINGLE(AVB2_AVTP_PPS),
/* TSN0 with MODSEL5 */
PINMUX_IPSR_NOGM(0, AVB2_TX_CTL, SEL_AVB2_TX_CTL_1),
PINMUX_IPSR_NOGM(0, AVB2_TXC, SEL_AVB2_TXC_1),
PINMUX_IPSR_NOGM(0, AVB2_TD0, SEL_AVB2_TD0_1),
PINMUX_IPSR_NOGM(0, AVB2_TD1, SEL_AVB2_TD1_1),
PINMUX_IPSR_NOGM(0, AVB2_TD2, SEL_AVB2_TD2_1),
PINMUX_IPSR_NOGM(0, AVB2_TD3, SEL_AVB2_TD3_1),
PINMUX_IPSR_NOGM(0, AVB2_MDC, SEL_AVB2_MDC_1),
PINMUX_IPSR_NOGM(0, AVB2_MAGIC, SEL_AVB2_MAGIC_1),
PINMUX_IPSR_NOGM(0, AVB2_AVTP_MATCH, SEL_AVB2_AVTP_MATCH_1),
PINMUX_IPSR_NOGM(0, AVB2_AVTP_PPS, SEL_AVB2_AVTP_PPS_1),
/* IP0SR0 */
PINMUX_IPSR_GPSR(IP0SR0_3_0, ERROROUTC_B),
@ -1030,23 +1032,23 @@ static const u16 pinmux_data[] = {
/* IP0SR6 */
PINMUX_IPSR_GPSR(IP0SR6_3_0, AVB1_MDIO),
PINMUX_IPSR_GPSR(IP0SR6_7_4, AVB1_MAGIC),
PINMUX_IPSR_MSEL(IP0SR6_7_4, AVB1_MAGIC, SEL_AVB1_MAGIC_1),
PINMUX_IPSR_GPSR(IP0SR6_11_8, AVB1_MDC),
PINMUX_IPSR_MSEL(IP0SR6_11_8, AVB1_MDC, SEL_AVB1_MDC_1),
PINMUX_IPSR_GPSR(IP0SR6_15_12, AVB1_PHY_INT),
PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_LINK),
PINMUX_IPSR_GPSR(IP0SR6_19_16, AVB1_MII_TX_ER),
PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_AVTP_MATCH),
PINMUX_IPSR_GPSR(IP0SR6_23_20, AVB1_MII_RX_ER),
PINMUX_IPSR_MSEL(IP0SR6_23_20, AVB1_AVTP_MATCH, SEL_AVB1_AVTP_MATCH_1),
PINMUX_IPSR_MSEL(IP0SR6_23_20, AVB1_MII_RX_ER, SEL_AVB1_AVTP_MATCH_0),
PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_TXC),
PINMUX_IPSR_GPSR(IP0SR6_27_24, AVB1_MII_TXC),
PINMUX_IPSR_MSEL(IP0SR6_27_24, AVB1_TXC, SEL_AVB1_TXC_1),
PINMUX_IPSR_MSEL(IP0SR6_27_24, AVB1_MII_TXC, SEL_AVB1_TXC_0),
PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_TX_CTL),
PINMUX_IPSR_GPSR(IP0SR6_31_28, AVB1_MII_TX_EN),
PINMUX_IPSR_MSEL(IP0SR6_31_28, AVB1_TX_CTL, SEL_AVB1_TX_CTL_1),
PINMUX_IPSR_MSEL(IP0SR6_31_28, AVB1_MII_TX_EN, SEL_AVB1_TX_CTL_0),
/* IP1SR6 */
PINMUX_IPSR_GPSR(IP1SR6_3_0, AVB1_RXC),
@ -1055,17 +1057,17 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_RX_CTL),
PINMUX_IPSR_GPSR(IP1SR6_7_4, AVB1_MII_RX_DV),
PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_AVTP_PPS),
PINMUX_IPSR_GPSR(IP1SR6_11_8, AVB1_MII_COL),
PINMUX_IPSR_MSEL(IP1SR6_11_8, AVB1_AVTP_PPS, SEL_AVB1_AVTP_PPS_1),
PINMUX_IPSR_MSEL(IP1SR6_11_8, AVB1_MII_COL, SEL_AVB1_AVTP_PPS_0),
PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_AVTP_CAPTURE),
PINMUX_IPSR_GPSR(IP1SR6_15_12, AVB1_MII_CRS),
PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_TD1),
PINMUX_IPSR_GPSR(IP1SR6_19_16, AVB1_MII_TD1),
PINMUX_IPSR_MSEL(IP1SR6_19_16, AVB1_TD1, SEL_AVB1_TD1_1),
PINMUX_IPSR_MSEL(IP1SR6_19_16, AVB1_MII_TD1, SEL_AVB1_TD1_0),
PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_TD0),
PINMUX_IPSR_GPSR(IP1SR6_23_20, AVB1_MII_TD0),
PINMUX_IPSR_MSEL(IP1SR6_23_20, AVB1_TD0, SEL_AVB1_TD0_1),
PINMUX_IPSR_MSEL(IP1SR6_23_20, AVB1_MII_TD0, SEL_AVB1_TD0_0),
PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_RD1),
PINMUX_IPSR_GPSR(IP1SR6_27_24, AVB1_MII_RD1),
@ -1074,14 +1076,14 @@ static const u16 pinmux_data[] = {
PINMUX_IPSR_GPSR(IP1SR6_31_28, AVB1_MII_RD0),
/* IP2SR6 */
PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_TD2),
PINMUX_IPSR_GPSR(IP2SR6_3_0, AVB1_MII_TD2),
PINMUX_IPSR_MSEL(IP2SR6_3_0, AVB1_TD2, SEL_AVB1_TD2_1),
PINMUX_IPSR_MSEL(IP2SR6_3_0, AVB1_MII_TD2, SEL_AVB1_TD2_0),
PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_RD2),
PINMUX_IPSR_GPSR(IP2SR6_7_4, AVB1_MII_RD2),
PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_TD3),
PINMUX_IPSR_GPSR(IP2SR6_11_8, AVB1_MII_TD3),
PINMUX_IPSR_MSEL(IP2SR6_11_8, AVB1_TD3, SEL_AVB1_TD3_1),
PINMUX_IPSR_MSEL(IP2SR6_11_8, AVB1_MII_TD3, SEL_AVB1_TD3_0),
PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_RD3),
PINMUX_IPSR_GPSR(IP2SR6_15_12, AVB1_MII_RD3),