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[TG3]: Add nvram detection for 5752
Signed-off-by: Michael Chan <mchan@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -7096,6 +7096,63 @@ static void __devinit tg3_get_nvram_info(struct tg3 *tp)
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}
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}
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static void __devinit tg3_get_5752_nvram_info(struct tg3 *tp)
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{
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u32 nvcfg1;
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nvcfg1 = tr32(NVRAM_CFG1);
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switch (nvcfg1 & NVRAM_CFG1_5752VENDOR_MASK) {
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case FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ:
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case FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ:
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tp->nvram_jedecnum = JEDEC_ATMEL;
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tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
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break;
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case FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED:
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tp->nvram_jedecnum = JEDEC_ATMEL;
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tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
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tp->tg3_flags2 |= TG3_FLG2_FLASH;
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break;
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case FLASH_5752VENDOR_ST_M45PE10:
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case FLASH_5752VENDOR_ST_M45PE20:
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case FLASH_5752VENDOR_ST_M45PE40:
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tp->nvram_jedecnum = JEDEC_ST;
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tp->tg3_flags |= TG3_FLAG_NVRAM_BUFFERED;
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tp->tg3_flags2 |= TG3_FLG2_FLASH;
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break;
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}
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if (tp->tg3_flags2 & TG3_FLG2_FLASH) {
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switch (nvcfg1 & NVRAM_CFG1_5752PAGE_SIZE_MASK) {
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case FLASH_5752PAGE_SIZE_256:
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tp->nvram_pagesize = 256;
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break;
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case FLASH_5752PAGE_SIZE_512:
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tp->nvram_pagesize = 512;
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break;
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case FLASH_5752PAGE_SIZE_1K:
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tp->nvram_pagesize = 1024;
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break;
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case FLASH_5752PAGE_SIZE_2K:
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tp->nvram_pagesize = 2048;
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break;
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case FLASH_5752PAGE_SIZE_4K:
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tp->nvram_pagesize = 4096;
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break;
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case FLASH_5752PAGE_SIZE_264:
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tp->nvram_pagesize = 264;
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break;
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}
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}
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else {
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/* For eeprom, set pagesize to maximum eeprom size */
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tp->nvram_pagesize = ATMEL_AT24C512_CHIP_SIZE;
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nvcfg1 &= ~NVRAM_CFG1_COMPAT_BYPASS;
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tw32(NVRAM_CFG1, nvcfg1);
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}
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}
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/* Chips other than 5700/5701 use the NVRAM for fetching info. */
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static void __devinit tg3_nvram_init(struct tg3 *tp)
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{
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@ -7128,7 +7185,11 @@ static void __devinit tg3_nvram_init(struct tg3 *tp)
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tw32(NVRAM_ACCESS, nvaccess | ACCESS_ENABLE);
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}
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tg3_get_nvram_info(tp);
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if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5752)
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tg3_get_5752_nvram_info(tp);
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else
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tg3_get_nvram_info(tp);
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tg3_get_nvram_size(tp);
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if (tp->tg3_flags2 & TG3_FLG2_5750_PLUS) {
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@ -1399,6 +1399,20 @@
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#define FLASH_VENDOR_SAIFUN 0x01000003
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#define FLASH_VENDOR_SST_SMALL 0x00000001
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#define FLASH_VENDOR_SST_LARGE 0x02000001
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#define NVRAM_CFG1_5752VENDOR_MASK 0x03c00003
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#define FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ 0x00000000
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#define FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ 0x02000000
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#define FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED 0x02000003
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#define FLASH_5752VENDOR_ST_M45PE10 0x02400000
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#define FLASH_5752VENDOR_ST_M45PE20 0x02400002
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#define FLASH_5752VENDOR_ST_M45PE40 0x02400001
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#define NVRAM_CFG1_5752PAGE_SIZE_MASK 0x70000000
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#define FLASH_5752PAGE_SIZE_256 0x00000000
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#define FLASH_5752PAGE_SIZE_512 0x10000000
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#define FLASH_5752PAGE_SIZE_1K 0x20000000
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#define FLASH_5752PAGE_SIZE_2K 0x30000000
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#define FLASH_5752PAGE_SIZE_4K 0x40000000
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#define FLASH_5752PAGE_SIZE_264 0x50000000
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#define NVRAM_CFG2 0x00007018
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#define NVRAM_CFG3 0x0000701c
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#define NVRAM_SWARB 0x00007020
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