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PCI: Cleanup register definition width and whitespace
Follow the file conventions of: - register offsets not indented - fields within a register indented one space - field masks use same width as register - register field values indented an additional space No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
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Bjorn Helgaas
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9e98c678c2
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35d0a06dad
@ -1,7 +1,5 @@
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/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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/*
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* pci_regs.h
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*
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* PCI standard defines
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* Copyright 1994, Drew Eckhardt
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* Copyright 1997--1999 Martin Mares <mj@ucw.cz>
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@ -15,7 +13,7 @@
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* PCI System Design Guide
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*
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* For HyperTransport information, please consult the following manuals
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* from http://www.hypertransport.org
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* from http://www.hypertransport.org :
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*
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* The HyperTransport I/O Link Specification
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*/
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@ -301,7 +299,7 @@
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#define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
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#define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
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/* Message Signalled Interrupts registers */
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/* Message Signalled Interrupt registers */
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#define PCI_MSI_FLAGS 2 /* Message Control */
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#define PCI_MSI_FLAGS_ENABLE 0x0001 /* MSI feature enabled */
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@ -319,7 +317,7 @@
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#define PCI_MSI_MASK_64 16 /* Mask bits register for 64-bit devices */
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#define PCI_MSI_PENDING_64 20 /* Pending intrs for 64-bit devices */
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/* MSI-X registers */
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/* MSI-X registers (in MSI-X capability) */
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#define PCI_MSIX_FLAGS 2 /* Message Control */
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#define PCI_MSIX_FLAGS_QSIZE 0x07FF /* Table size */
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#define PCI_MSIX_FLAGS_MASKALL 0x4000 /* Mask all vectors for this function */
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@ -333,13 +331,13 @@
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#define PCI_MSIX_FLAGS_BIRMASK PCI_MSIX_PBA_BIR /* deprecated */
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#define PCI_CAP_MSIX_SIZEOF 12 /* size of MSIX registers */
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/* MSI-X Table entry format */
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/* MSI-X Table entry format (in memory mapped by a BAR) */
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#define PCI_MSIX_ENTRY_SIZE 16
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#define PCI_MSIX_ENTRY_LOWER_ADDR 0
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#define PCI_MSIX_ENTRY_UPPER_ADDR 4
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#define PCI_MSIX_ENTRY_DATA 8
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#define PCI_MSIX_ENTRY_VECTOR_CTRL 12
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#define PCI_MSIX_ENTRY_CTRL_MASKBIT 1
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#define PCI_MSIX_ENTRY_LOWER_ADDR 0 /* Message Address */
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#define PCI_MSIX_ENTRY_UPPER_ADDR 4 /* Message Upper Address */
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#define PCI_MSIX_ENTRY_DATA 8 /* Message Data */
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#define PCI_MSIX_ENTRY_VECTOR_CTRL 12 /* Vector Control */
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#define PCI_MSIX_ENTRY_CTRL_MASKBIT 0x00000001
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/* CompactPCI Hotswap Register */
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@ -465,19 +463,19 @@
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/* PCI Express capability registers */
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#define PCI_EXP_FLAGS 2 /* Capabilities register */
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#define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
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#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
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#define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
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#define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
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#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
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#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
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#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
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#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCIe to PCI/PCI-X Bridge */
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#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIe Bridge */
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#define PCI_EXP_TYPE_RC_END 0x9 /* Root Complex Integrated Endpoint */
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#define PCI_EXP_TYPE_RC_EC 0xa /* Root Complex Event Collector */
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#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
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#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
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#define PCI_EXP_FLAGS_VERS 0x000f /* Capability version */
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#define PCI_EXP_FLAGS_TYPE 0x00f0 /* Device/Port type */
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#define PCI_EXP_TYPE_ENDPOINT 0x0 /* Express Endpoint */
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#define PCI_EXP_TYPE_LEG_END 0x1 /* Legacy Endpoint */
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#define PCI_EXP_TYPE_ROOT_PORT 0x4 /* Root Port */
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#define PCI_EXP_TYPE_UPSTREAM 0x5 /* Upstream Port */
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#define PCI_EXP_TYPE_DOWNSTREAM 0x6 /* Downstream Port */
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#define PCI_EXP_TYPE_PCI_BRIDGE 0x7 /* PCIe to PCI/PCI-X Bridge */
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#define PCI_EXP_TYPE_PCIE_BRIDGE 0x8 /* PCI/PCI-X to PCIe Bridge */
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#define PCI_EXP_TYPE_RC_END 0x9 /* Root Complex Integrated Endpoint */
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#define PCI_EXP_TYPE_RC_EC 0xa /* Root Complex Event Collector */
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#define PCI_EXP_FLAGS_SLOT 0x0100 /* Slot implemented */
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#define PCI_EXP_FLAGS_IRQ 0x3e00 /* Interrupt message number */
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#define PCI_EXP_DEVCAP 4 /* Device capabilities */
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#define PCI_EXP_DEVCAP_PAYLOAD 0x00000007 /* Max_Payload_Size */
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#define PCI_EXP_DEVCAP_PHANTOM 0x00000018 /* Phantom functions */
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@ -616,8 +614,8 @@
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#define PCI_EXP_RTCAP 30 /* Root Capabilities */
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#define PCI_EXP_RTCAP_CRSVIS 0x0001 /* CRS Software Visibility capability */
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#define PCI_EXP_RTSTA 32 /* Root Status */
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#define PCI_EXP_RTSTA_PME 0x00010000 /* PME status */
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#define PCI_EXP_RTSTA_PENDING 0x00020000 /* PME pending */
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#define PCI_EXP_RTSTA_PME 0x00010000 /* PME status */
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#define PCI_EXP_RTSTA_PENDING 0x00020000 /* PME pending */
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/*
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* The Device Capabilities 2, Device Status 2, Device Control 2,
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* Link Capabilities 2, Link Status 2, Link Control 2,
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@ -637,13 +635,13 @@
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#define PCI_EXP_DEVCAP2_OBFF_MASK 0x000c0000 /* OBFF support mechanism */
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#define PCI_EXP_DEVCAP2_OBFF_MSG 0x00040000 /* New message signaling */
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#define PCI_EXP_DEVCAP2_OBFF_WAKE 0x00080000 /* Re-use WAKE# for OBFF */
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#define PCI_EXP_DEVCAP2_EE_PREFIX 0x00200000 /* End-End TLP Prefix */
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#define PCI_EXP_DEVCAP2_EE_PREFIX 0x00200000 /* End-End TLP Prefix */
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#define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
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#define PCI_EXP_DEVCTL2_COMP_TIMEOUT 0x000f /* Completion Timeout Value */
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#define PCI_EXP_DEVCTL2_COMP_TMOUT_DIS 0x0010 /* Completion Timeout Disable */
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#define PCI_EXP_DEVCTL2_ARI 0x0020 /* Alternative Routing-ID */
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#define PCI_EXP_DEVCTL2_ATOMIC_REQ 0x0040 /* Set Atomic requests */
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#define PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK 0x0080 /* Block atomic egress */
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#define PCI_EXP_DEVCTL2_ATOMIC_REQ 0x0040 /* Set Atomic requests */
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#define PCI_EXP_DEVCTL2_ATOMIC_EGRESS_BLOCK 0x0080 /* Block atomic egress */
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#define PCI_EXP_DEVCTL2_IDO_REQ_EN 0x0100 /* Allow IDO for requests */
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#define PCI_EXP_DEVCTL2_IDO_CMP_EN 0x0200 /* Allow IDO for completions */
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#define PCI_EXP_DEVCTL2_LTR_EN 0x0400 /* Enable LTR mechanism */
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@ -659,11 +657,11 @@
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#define PCI_EXP_LNKCAP2_SLS_16_0GB 0x00000010 /* Supported Speed 16GT/s */
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#define PCI_EXP_LNKCAP2_CROSSLINK 0x00000100 /* Crosslink supported */
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#define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
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#define PCI_EXP_LNKCTL2_TLS 0x000f
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#define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */
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#define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */
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#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */
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#define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */
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#define PCI_EXP_LNKCTL2_TLS 0x000f
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#define PCI_EXP_LNKCTL2_TLS_2_5GT 0x0001 /* Supported Speed 2.5GT/s */
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#define PCI_EXP_LNKCTL2_TLS_5_0GT 0x0002 /* Supported Speed 5GT/s */
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#define PCI_EXP_LNKCTL2_TLS_8_0GT 0x0003 /* Supported Speed 8GT/s */
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#define PCI_EXP_LNKCTL2_TLS_16_0GT 0x0004 /* Supported Speed 16GT/s */
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#define PCI_EXP_LNKSTA2 50 /* Link Status 2 */
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#define PCI_CAP_EXP_ENDPOINT_SIZEOF_V2 52 /* v2 endpoints with link end here */
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#define PCI_EXP_SLTCAP2 52 /* Slot Capabilities 2 */
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@ -752,18 +750,18 @@
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#define PCI_ERR_CAP_ECRC_CHKE 0x00000100 /* ECRC Check Enable */
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#define PCI_ERR_HEADER_LOG 28 /* Header Log Register (16 bytes) */
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#define PCI_ERR_ROOT_COMMAND 44 /* Root Error Command */
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#define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 /* Correctable Err Reporting Enable */
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#define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 /* Non-Fatal Err Reporting Enable */
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#define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004 /* Fatal Err Reporting Enable */
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#define PCI_ERR_ROOT_CMD_COR_EN 0x00000001 /* Correctable Err Reporting Enable */
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#define PCI_ERR_ROOT_CMD_NONFATAL_EN 0x00000002 /* Non-Fatal Err Reporting Enable */
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#define PCI_ERR_ROOT_CMD_FATAL_EN 0x00000004 /* Fatal Err Reporting Enable */
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#define PCI_ERR_ROOT_STATUS 48
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#define PCI_ERR_ROOT_COR_RCV 0x00000001 /* ERR_COR Received */
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#define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 /* Multiple ERR_COR */
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#define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 /* ERR_FATAL/NONFATAL */
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#define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 /* Multiple FATAL/NONFATAL */
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#define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First UNC is Fatal */
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#define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */
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#define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */
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#define PCI_ERR_ROOT_AER_IRQ 0xf8000000 /* Advanced Error Interrupt Message Number */
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#define PCI_ERR_ROOT_COR_RCV 0x00000001 /* ERR_COR Received */
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#define PCI_ERR_ROOT_MULTI_COR_RCV 0x00000002 /* Multiple ERR_COR */
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#define PCI_ERR_ROOT_UNCOR_RCV 0x00000004 /* ERR_FATAL/NONFATAL */
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#define PCI_ERR_ROOT_MULTI_UNCOR_RCV 0x00000008 /* Multiple FATAL/NONFATAL */
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#define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First UNC is Fatal */
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#define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */
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#define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */
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#define PCI_ERR_ROOT_AER_IRQ 0xf8000000 /* Advanced Error Interrupt Message Number */
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#define PCI_ERR_ROOT_ERR_SRC 52 /* Error Source Identification */
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/* Virtual Channel */
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@ -875,12 +873,12 @@
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/* Page Request Interface */
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#define PCI_PRI_CTRL 0x04 /* PRI control register */
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#define PCI_PRI_CTRL_ENABLE 0x01 /* Enable */
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#define PCI_PRI_CTRL_RESET 0x02 /* Reset */
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#define PCI_PRI_CTRL_ENABLE 0x0001 /* Enable */
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#define PCI_PRI_CTRL_RESET 0x0002 /* Reset */
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#define PCI_PRI_STATUS 0x06 /* PRI status register */
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#define PCI_PRI_STATUS_RF 0x001 /* Response Failure */
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#define PCI_PRI_STATUS_UPRGI 0x002 /* Unexpected PRG index */
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#define PCI_PRI_STATUS_STOPPED 0x100 /* PRI Stopped */
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#define PCI_PRI_STATUS_RF 0x0001 /* Response Failure */
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#define PCI_PRI_STATUS_UPRGI 0x0002 /* Unexpected PRG index */
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#define PCI_PRI_STATUS_STOPPED 0x0100 /* PRI Stopped */
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#define PCI_PRI_STATUS_PASID 0x8000 /* PRG Response PASID Required */
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#define PCI_PRI_MAX_REQ 0x08 /* PRI max reqs supported */
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#define PCI_PRI_ALLOC_REQ 0x0c /* PRI max reqs allowed */
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@ -898,16 +896,16 @@
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/* Single Root I/O Virtualization */
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#define PCI_SRIOV_CAP 0x04 /* SR-IOV Capabilities */
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#define PCI_SRIOV_CAP_VFM 0x01 /* VF Migration Capable */
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#define PCI_SRIOV_CAP_VFM 0x00000001 /* VF Migration Capable */
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#define PCI_SRIOV_CAP_INTR(x) ((x) >> 21) /* Interrupt Message Number */
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#define PCI_SRIOV_CTRL 0x08 /* SR-IOV Control */
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#define PCI_SRIOV_CTRL_VFE 0x01 /* VF Enable */
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#define PCI_SRIOV_CTRL_VFM 0x02 /* VF Migration Enable */
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#define PCI_SRIOV_CTRL_INTR 0x04 /* VF Migration Interrupt Enable */
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#define PCI_SRIOV_CTRL_MSE 0x08 /* VF Memory Space Enable */
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#define PCI_SRIOV_CTRL_ARI 0x10 /* ARI Capable Hierarchy */
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#define PCI_SRIOV_CTRL_VFE 0x0001 /* VF Enable */
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#define PCI_SRIOV_CTRL_VFM 0x0002 /* VF Migration Enable */
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#define PCI_SRIOV_CTRL_INTR 0x0004 /* VF Migration Interrupt Enable */
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#define PCI_SRIOV_CTRL_MSE 0x0008 /* VF Memory Space Enable */
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#define PCI_SRIOV_CTRL_ARI 0x0010 /* ARI Capable Hierarchy */
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#define PCI_SRIOV_STATUS 0x0a /* SR-IOV Status */
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#define PCI_SRIOV_STATUS_VFM 0x01 /* VF Migration Status */
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#define PCI_SRIOV_STATUS_VFM 0x0001 /* VF Migration Status */
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#define PCI_SRIOV_INITIAL_VF 0x0c /* Initial VFs */
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#define PCI_SRIOV_TOTAL_VF 0x0e /* Total VFs */
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#define PCI_SRIOV_NUM_VF 0x10 /* Number of VFs */
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@ -937,13 +935,13 @@
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/* Access Control Service */
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#define PCI_ACS_CAP 0x04 /* ACS Capability Register */
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#define PCI_ACS_SV 0x01 /* Source Validation */
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#define PCI_ACS_TB 0x02 /* Translation Blocking */
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#define PCI_ACS_RR 0x04 /* P2P Request Redirect */
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#define PCI_ACS_CR 0x08 /* P2P Completion Redirect */
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#define PCI_ACS_UF 0x10 /* Upstream Forwarding */
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#define PCI_ACS_EC 0x20 /* P2P Egress Control */
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#define PCI_ACS_DT 0x40 /* Direct Translated P2P */
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#define PCI_ACS_SV 0x0001 /* Source Validation */
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#define PCI_ACS_TB 0x0002 /* Translation Blocking */
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#define PCI_ACS_RR 0x0004 /* P2P Request Redirect */
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#define PCI_ACS_CR 0x0008 /* P2P Completion Redirect */
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#define PCI_ACS_UF 0x0010 /* Upstream Forwarding */
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#define PCI_ACS_EC 0x0020 /* P2P Egress Control */
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#define PCI_ACS_DT 0x0040 /* Direct Translated P2P */
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#define PCI_ACS_EGRESS_BITS 0x05 /* ACS Egress Control Vector Size */
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#define PCI_ACS_CTRL 0x06 /* ACS Control Register */
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#define PCI_ACS_EGRESS_CTL_V 0x08 /* ACS Egress Control Vector */
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@ -993,9 +991,9 @@
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#define PCI_EXP_DPC_CAP_DL_ACTIVE 0x1000 /* ERR_COR signal on DL_Active supported */
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#define PCI_EXP_DPC_CTL 6 /* DPC control */
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#define PCI_EXP_DPC_CTL_EN_FATAL 0x0001 /* Enable trigger on ERR_FATAL message */
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#define PCI_EXP_DPC_CTL_EN_NONFATAL 0x0002 /* Enable trigger on ERR_NONFATAL message */
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#define PCI_EXP_DPC_CTL_INT_EN 0x0008 /* DPC Interrupt Enable */
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#define PCI_EXP_DPC_CTL_EN_FATAL 0x0001 /* Enable trigger on ERR_FATAL message */
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#define PCI_EXP_DPC_CTL_EN_NONFATAL 0x0002 /* Enable trigger on ERR_NONFATAL message */
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#define PCI_EXP_DPC_CTL_INT_EN 0x0008 /* DPC Interrupt Enable */
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#define PCI_EXP_DPC_STATUS 8 /* DPC Status */
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#define PCI_EXP_DPC_STATUS_TRIGGER 0x0001 /* Trigger Status */
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