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powerpc: Add interrupt support to mpc8xxx_gpio
Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk> Acked-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
This commit is contained in:
Peter Korsgaard
Kumar Gala
parent
1ed31d6db9
commit
345e5c8a1c
@ -11,7 +11,7 @@ Required properties:
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83xx, "fsl,mpc8572-gpio" for 85xx and "fsl,mpc8610-gpio" for 86xx.
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- #gpio-cells : Should be two. The first cell is the pin number and the
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second cell is used to specify optional parameters (currently unused).
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- interrupts : Interrupt mapping for GPIO IRQ (currently unused).
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- interrupts : Interrupt mapping for GPIO IRQ.
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- interrupt-parent : Phandle for the interrupt controller that
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services interrupts for this device.
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- gpio-controller : Marks the port as GPIO controller.
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@ -38,3 +38,23 @@ Example of gpio-controller nodes for a MPC8347 SoC:
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See booting-without-of.txt for details of how to specify GPIO
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information for devices.
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To use GPIO pins as interrupt sources for peripherals, specify the
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GPIO controller as the interrupt parent and define GPIO number +
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trigger mode using the interrupts property, which is defined like
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this:
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interrupts = <number trigger>, where:
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- number: GPIO pin (0..31)
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- trigger: trigger mode:
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2 = trigger on falling edge
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3 = trigger on both edges
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Example of device using this is:
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funkyfpga@0 {
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compatible = "funky-fpga";
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...
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interrupts = <4 3>;
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interrupt-parent = <&gpio1>;
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};
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@ -16,6 +16,7 @@
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#include <linux/of_gpio.h>
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#include <linux/gpio.h>
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#include <linux/slab.h>
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#include <linux/irq.h>
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#define MPC8XXX_GPIO_PINS 32
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@ -35,6 +36,7 @@ struct mpc8xxx_gpio_chip {
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* open drain mode safely
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*/
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u32 data;
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struct irq_host *irq;
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};
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static inline u32 mpc8xxx_gpio2mask(unsigned int gpio)
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@ -128,12 +130,136 @@ static int mpc8xxx_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val
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return 0;
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}
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static int mpc8xxx_gpio_to_irq(struct gpio_chip *gc, unsigned offset)
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{
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struct of_mm_gpio_chip *mm = to_of_mm_gpio_chip(gc);
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = to_mpc8xxx_gpio_chip(mm);
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if (mpc8xxx_gc->irq && offset < MPC8XXX_GPIO_PINS)
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return irq_create_mapping(mpc8xxx_gc->irq, offset);
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else
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return -ENXIO;
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}
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static void mpc8xxx_gpio_irq_cascade(unsigned int irq, struct irq_desc *desc)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_desc_data(desc);
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struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
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unsigned int mask;
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mask = in_be32(mm->regs + GPIO_IER) & in_be32(mm->regs + GPIO_IMR);
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if (mask)
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generic_handle_irq(irq_linear_revmap(mpc8xxx_gc->irq,
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32 - ffs(mask)));
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}
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static void mpc8xxx_irq_unmask(unsigned int virq)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_chip_data(virq);
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struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
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unsigned long flags;
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spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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setbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(virq_to_hw(virq)));
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spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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}
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static void mpc8xxx_irq_mask(unsigned int virq)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_chip_data(virq);
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struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
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unsigned long flags;
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spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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clrbits32(mm->regs + GPIO_IMR, mpc8xxx_gpio2mask(virq_to_hw(virq)));
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spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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}
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static void mpc8xxx_irq_ack(unsigned int virq)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_chip_data(virq);
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struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
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out_be32(mm->regs + GPIO_IER, mpc8xxx_gpio2mask(virq_to_hw(virq)));
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}
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static int mpc8xxx_irq_set_type(unsigned int virq, unsigned int flow_type)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc = get_irq_chip_data(virq);
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struct of_mm_gpio_chip *mm = &mpc8xxx_gc->mm_gc;
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unsigned long flags;
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switch (flow_type) {
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case IRQ_TYPE_EDGE_FALLING:
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spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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setbits32(mm->regs + GPIO_ICR,
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mpc8xxx_gpio2mask(virq_to_hw(virq)));
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spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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break;
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case IRQ_TYPE_EDGE_BOTH:
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spin_lock_irqsave(&mpc8xxx_gc->lock, flags);
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clrbits32(mm->regs + GPIO_ICR,
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mpc8xxx_gpio2mask(virq_to_hw(virq)));
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spin_unlock_irqrestore(&mpc8xxx_gc->lock, flags);
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static struct irq_chip mpc8xxx_irq_chip = {
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.name = "mpc8xxx-gpio",
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.unmask = mpc8xxx_irq_unmask,
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.mask = mpc8xxx_irq_mask,
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.ack = mpc8xxx_irq_ack,
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.set_type = mpc8xxx_irq_set_type,
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};
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static int mpc8xxx_gpio_irq_map(struct irq_host *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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set_irq_chip_data(virq, h->host_data);
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set_irq_chip_and_handler(virq, &mpc8xxx_irq_chip, handle_level_irq);
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set_irq_type(virq, IRQ_TYPE_NONE);
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return 0;
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}
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static int mpc8xxx_gpio_irq_xlate(struct irq_host *h, struct device_node *ct,
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const u32 *intspec, unsigned int intsize,
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irq_hw_number_t *out_hwirq,
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unsigned int *out_flags)
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{
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/* interrupt sense values coming from the device tree equal either
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* EDGE_FALLING or EDGE_BOTH
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*/
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*out_hwirq = intspec[0];
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*out_flags = intspec[1];
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return 0;
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}
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static struct irq_host_ops mpc8xxx_gpio_irq_ops = {
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.map = mpc8xxx_gpio_irq_map,
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.xlate = mpc8xxx_gpio_irq_xlate,
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};
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static void __init mpc8xxx_add_controller(struct device_node *np)
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{
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struct mpc8xxx_gpio_chip *mpc8xxx_gc;
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struct of_mm_gpio_chip *mm_gc;
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struct of_gpio_chip *of_gc;
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struct gpio_chip *gc;
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unsigned hwirq;
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int ret;
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mpc8xxx_gc = kzalloc(sizeof(*mpc8xxx_gc), GFP_KERNEL);
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@ -158,11 +284,32 @@ static void __init mpc8xxx_add_controller(struct device_node *np)
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else
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gc->get = mpc8xxx_gpio_get;
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gc->set = mpc8xxx_gpio_set;
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gc->to_irq = mpc8xxx_gpio_to_irq;
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ret = of_mm_gpiochip_add(np, mm_gc);
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if (ret)
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goto err;
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hwirq = irq_of_parse_and_map(np, 0);
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if (hwirq == NO_IRQ)
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goto skip_irq;
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mpc8xxx_gc->irq =
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irq_alloc_host(np, IRQ_HOST_MAP_LINEAR, MPC8XXX_GPIO_PINS,
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&mpc8xxx_gpio_irq_ops, MPC8XXX_GPIO_PINS);
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if (!mpc8xxx_gc->irq)
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goto skip_irq;
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mpc8xxx_gc->irq->host_data = mpc8xxx_gc;
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/* ack and mask all irqs */
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out_be32(mm_gc->regs + GPIO_IER, 0xffffffff);
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out_be32(mm_gc->regs + GPIO_IMR, 0);
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set_irq_data(hwirq, mpc8xxx_gc);
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set_irq_chained_handler(hwirq, mpc8xxx_gpio_irq_cascade);
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skip_irq:
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return;
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err:
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