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coresight: etm4x: Fix save/restore during cpu idle
The ETM state save/restore incorrectly reads/writes some of the 64bit
registers (e.g, address comparators, vmid/cid comparators etc.) using
32bit accesses. Ensure we use the appropriate width accessors for
the registers.
Fixes: f188b5e76a
("coresight: etm4x: Save/restore state across CPU low power states")
Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
Cc: Mike Leach <mike.leach@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Link: https://lore.kernel.org/r/20200716175746.3338735-18-mathieu.poirier@linaro.org
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
parent
bbfb8f3e4e
commit
342c8a1d1d
@ -1206,8 +1206,8 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
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}
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for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
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state->trcacvr[i] = readl(drvdata->base + TRCACVRn(i));
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state->trcacatr[i] = readl(drvdata->base + TRCACATRn(i));
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state->trcacvr[i] = readq(drvdata->base + TRCACVRn(i));
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state->trcacatr[i] = readq(drvdata->base + TRCACATRn(i));
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}
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/*
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@ -1218,10 +1218,10 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
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*/
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for (i = 0; i < drvdata->numcidc; i++)
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state->trccidcvr[i] = readl(drvdata->base + TRCCIDCVRn(i));
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state->trccidcvr[i] = readq(drvdata->base + TRCCIDCVRn(i));
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for (i = 0; i < drvdata->numvmidc; i++)
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state->trcvmidcvr[i] = readl(drvdata->base + TRCVMIDCVRn(i));
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state->trcvmidcvr[i] = readq(drvdata->base + TRCVMIDCVRn(i));
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state->trccidcctlr0 = readl(drvdata->base + TRCCIDCCTLR0);
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state->trccidcctlr1 = readl(drvdata->base + TRCCIDCCTLR1);
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@ -1319,18 +1319,18 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
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}
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for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
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writel_relaxed(state->trcacvr[i],
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writeq_relaxed(state->trcacvr[i],
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drvdata->base + TRCACVRn(i));
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writel_relaxed(state->trcacatr[i],
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writeq_relaxed(state->trcacatr[i],
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drvdata->base + TRCACATRn(i));
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}
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for (i = 0; i < drvdata->numcidc; i++)
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writel_relaxed(state->trccidcvr[i],
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writeq_relaxed(state->trccidcvr[i],
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drvdata->base + TRCCIDCVRn(i));
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for (i = 0; i < drvdata->numvmidc; i++)
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writel_relaxed(state->trcvmidcvr[i],
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writeq_relaxed(state->trcvmidcvr[i],
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drvdata->base + TRCVMIDCVRn(i));
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writel_relaxed(state->trccidcctlr0, drvdata->base + TRCCIDCCTLR0);
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@ -334,7 +334,7 @@ struct etmv4_save_state {
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u64 trcacvr[ETM_MAX_SINGLE_ADDR_CMP];
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u64 trcacatr[ETM_MAX_SINGLE_ADDR_CMP];
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u64 trccidcvr[ETMv4_MAX_CTXID_CMP];
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u32 trcvmidcvr[ETM_MAX_VMID_CMP];
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u64 trcvmidcvr[ETM_MAX_VMID_CMP];
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u32 trccidcctlr0;
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u32 trccidcctlr1;
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u32 trcvmidcctlr0;
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