mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-24 19:45:06 +08:00
drm/i915: drop WaMbcDriverBootEnable workaround
Turns out the BIOS will do this for us as needed, and if we try to do it again we risk hangs or other bad behavior. Note that this seems to break libva on ChromeOS after resumes (but strangely _not_ after booting up). This essentially reverts commitb4ae3f22d2
Author: Jesse Barnes <jbarnes@virtuousgeek.org> Date: Thu Jun 14 11:04:48 2012 -0700 drm/i915: load boot context at driver init time and commitb3bf076697
Author: Paulo Zanoni <paulo.r.zanoni@intel.com> Date: Tue Nov 20 13:27:44 2012 -0200 drm/i915: implement WaMbcDriverBootEnable on Haswell Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org> Reported-and-Tested-by: Stéphane Marchesin <marcheu@chromium.org> [danvet: Add note about impact and regression citation.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
This commit is contained in:
parent
5032d871f7
commit
3414caf634
@ -4864,10 +4864,6 @@ static void gen6_init_clock_gating(struct drm_device *dev)
|
||||
ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
|
||||
ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
|
||||
|
||||
/* WaMbcDriverBootEnable:snb */
|
||||
I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
|
||||
GEN6_MBCTL_ENABLE_BOOT_FETCH);
|
||||
|
||||
g4x_disable_trickle_feed(dev);
|
||||
|
||||
/* The default value should be 0x200 according to docs, but the two
|
||||
@ -4963,10 +4959,6 @@ static void haswell_init_clock_gating(struct drm_device *dev)
|
||||
I915_WRITE(CACHE_MODE_1,
|
||||
_MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
|
||||
|
||||
/* WaMbcDriverBootEnable:hsw */
|
||||
I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
|
||||
GEN6_MBCTL_ENABLE_BOOT_FETCH);
|
||||
|
||||
/* WaSwitchSolVfFArbitrationPriority:hsw */
|
||||
I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
|
||||
|
||||
@ -5050,10 +5042,6 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
|
||||
|
||||
g4x_disable_trickle_feed(dev);
|
||||
|
||||
/* WaMbcDriverBootEnable:ivb */
|
||||
I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
|
||||
GEN6_MBCTL_ENABLE_BOOT_FETCH);
|
||||
|
||||
/* WaVSRefCountFullforceMissDisable:ivb */
|
||||
gen7_setup_fixed_func_scheduler(dev_priv);
|
||||
|
||||
@ -5113,11 +5101,6 @@ static void valleyview_init_clock_gating(struct drm_device *dev)
|
||||
I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
|
||||
GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
|
||||
|
||||
/* WaMbcDriverBootEnable:vlv */
|
||||
I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
|
||||
GEN6_MBCTL_ENABLE_BOOT_FETCH);
|
||||
|
||||
|
||||
/* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
|
||||
* gating disable must be set. Failure to set it results in
|
||||
* flickering pixels due to Z write ordering failures after
|
||||
|
Loading…
Reference in New Issue
Block a user