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More ACPI updates for 5.9-rc1

Browse Source 
Add new hardware support to the ACPI driver for AMD SoCs, the x86 clk
 driver and the Designware i2c driver (changes from Akshu Agrawal and
 Pu Wen).
 -----BEGIN PGP SIGNATURE-----
 
 iQJGBAABCAAwFiEE4fcc61cGeeHD/fCwgsRv/nhiVHEFAl820JQSHHJqd0Byand5
 c29ja2kubmV0AAoJEILEb/54YlRxy2wP/jXaIw3YtMhDeu0V9qsODq4BuDEW4wV+
 ZaKny6fz1AVekhdH/0BUh4GdgSJQMyuKpL3i0SPJamkykwQSxQnGo6X8g7NWwjQF
 d0HPNW7QOJE1B9gyLKj7zI5RRVwXSAHJxO3651QH+0CUcNHggFRGEXYGCEukvJBz
 CM5ZxMRaFOTvqHVu38cmL7LFNveO8dO1V4SKAQzsOpipW8//noxC/eaE86Rg2Zk/
 1x3F5jBv07Cdt7JJOO44PEKyH6uNU7tkfkfGKeEiWxi+b+CiSpvJPMCgOS6eb/gS
 mBTVMXvB5IuLcXvG3ftr2gVbl87bh27wUmcQyJuLNfj6tEsVwz3rvPd6aRpXmu1R
 xnto4R8FPnIGb5XFKU1fbOgQwueliKAVt0mhfi8AYJUshpC3jtPtfJeH8dumPBp4
 ZfBu8h7uk77mpunQ8B8VL/+Kj5f7kiQ5hRWRBxv2KPQMdljy1ufeQbWAgc+XY/EG
 eSzo8qxdRs6PGWfXVDVZu3hCMJ+nSzY/GsBJ0z/p7+29HGczQZdYPMU0iWoM6DMS
 dSq8/+4m1JReA3HGdgbgBVs3EH0V/zReCAR6bdAFvFuAAubm2mXQfliVzhdNVDQ2
 7MVxuhU11p7CEwp5i+UZNvJ11KT2oyqHtboLkqNBHMm2fnRZBTUL05wLEP35adj9
 WwK7n2XpSKc0
 =D9q+
 -----END PGP SIGNATURE-----

Merge tag 'acpi-5.9-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm

Pull more ACPI updates from Rafael Wysocki:
 "Add new hardware support to the ACPI driver for AMD SoCs, the x86 clk
  driver and the Designware i2c driver (changes from Akshu Agrawal and
  Pu Wen)"

* tag 'acpi-5.9-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm:
  clk: x86: Support RV architecture
  ACPI: APD: Add a fmw property is_raven
  clk: x86: Change name from ST to FCH
  ACPI: APD: Change name from ST to FCH
  i2c: designware: Add device HID for Hygon I2C controller
This commit is contained in:
Linus Torvalds 2020-08-15 08:18:22 -07:00
commit 341323fa0e
6 changed files with 121 additions and 91 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
drivers/acpi/acpi_apd.c
View File

@ -8,7 +8,7 @@
*/
#include <linux/clk-provider.h>
#include <linux/platform_data/clk-st.h>
#include <linux/platform_data/clk-fch.h>
#include <linux/platform_device.h>
#include <linux/pm_domain.h>
#include <linux/clkdev.h>
@ -79,11 +79,12 @@ static int misc_check_res(struct acpi_resource *ares, void *data)
return !acpi_dev_resource_memory(ares, &res);
}
static int st_misc_setup(struct apd_private_data *pdata)
static int fch_misc_setup(struct apd_private_data *pdata)
{
struct acpi_device *adev = pdata->adev;
const union acpi_object *obj;
struct platform_device *clkdev;
struct st_clk_data *clk_data;
struct fch_clk_data *clk_data;
struct resource_entry *rentry;
struct list_head resource_list;
int ret;
@ -98,6 +99,9 @@ static int st_misc_setup(struct apd_private_data *pdata)
if (ret < 0)
return -ENOENT;
acpi_dev_get_property(adev, "is-rv", ACPI_TYPE_INTEGER, &obj);
clk_data->is_rv = obj->integer.value;
list_for_each_entry(rentry, &resource_list, node) {
clk_data->base = devm_ioremap(&adev->dev, rentry->res->start,
resource_size(rentry->res));
@ -106,7 +110,7 @@ static int st_misc_setup(struct apd_private_data *pdata)
acpi_dev_free_resource_list(&resource_list);
clkdev = platform_device_register_data(&adev->dev, "clk-st",
clkdev = platform_device_register_data(&adev->dev, "clk-fch",
PLATFORM_DEVID_NONE, clk_data,
sizeof(*clk_data));
return PTR_ERR_OR_ZERO(clkdev);
@ -135,8 +139,8 @@ static const struct apd_device_desc cz_uart_desc = {
.properties = uart_properties,
};
static const struct apd_device_desc st_misc_desc = {
.setup = st_misc_setup,
static const struct apd_device_desc fch_misc_desc = {
.setup = fch_misc_setup,
};
#endif
@ -239,7 +243,8 @@ static const struct acpi_device_id acpi_apd_device_ids[] = {
{ "AMD0020", APD_ADDR(cz_uart_desc) },
{ "AMDI0020", APD_ADDR(cz_uart_desc) },
{ "AMD0030", },
{ "AMD0040", APD_ADDR(st_misc_desc)},
{ "AMD0040", APD_ADDR(fch_misc_desc)},
{ "HYGO0010", APD_ADDR(wt_i2c_desc) },
#endif
#ifdef CONFIG_ARM64
{ "APMC0D0F", APD_ADDR(xgene_i2c_desc) },

2
drivers/clk/x86/Makefile
View File

@ -1,6 +1,6 @@
# SPDX-License-Identifier: GPL-2.0-only
obj-$(CONFIG_PMC_ATOM) += clk-pmc-atom.o
obj-$(CONFIG_X86_AMD_PLATFORM_DEVICE) += clk-st.o
obj-$(CONFIG_X86_AMD_PLATFORM_DEVICE) += clk-fch.o
clk-x86-lpss-objs := clk-lpt.o
obj-$(CONFIG_X86_INTEL_LPSS) += clk-x86-lpss.o
obj-$(CONFIG_CLK_LGM_CGU) += clk-cgu.o clk-cgu-pll.o clk-lgm.o

101
drivers/clk/x86/clk-fch.c Normal file
View File

@ -0,0 +1,101 @@
// SPDX-License-Identifier: MIT
/*
* clock framework for AMD Stoney based clocks
*
* Copyright 2018 Advanced Micro Devices, Inc.
*/
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/platform_data/clk-fch.h>
#include <linux/platform_device.h>
/* Clock Driving Strength 2 register */
#define CLKDRVSTR2 0x28
/* Clock Control 1 register */
#define MISCCLKCNTL1 0x40
/* Auxiliary clock1 enable bit */
#define OSCCLKENB 2
/* 25Mhz auxiliary output clock freq bit */
#define OSCOUT1CLK25MHZ 16
#define ST_CLK_48M 0
#define ST_CLK_25M 1
#define ST_CLK_MUX 2
#define ST_CLK_GATE 3
#define ST_MAX_CLKS 4
#define RV_CLK_48M 0
#define RV_CLK_GATE 1
#define RV_MAX_CLKS 2
static const char * const clk_oscout1_parents[] = { "clk48MHz", "clk25MHz" };
static struct clk_hw *hws[ST_MAX_CLKS];
static int fch_clk_probe(struct platform_device *pdev)
{
struct fch_clk_data *fch_data;
fch_data = dev_get_platdata(&pdev->dev);
if (!fch_data || !fch_data->base)
return -EINVAL;
if (!fch_data->is_rv) {
hws[ST_CLK_48M] = clk_hw_register_fixed_rate(NULL, "clk48MHz",
NULL, 0, 48000000);
hws[ST_CLK_25M] = clk_hw_register_fixed_rate(NULL, "clk25MHz",
NULL, 0, 25000000);
hws[ST_CLK_MUX] = clk_hw_register_mux(NULL, "oscout1_mux",
clk_oscout1_parents, ARRAY_SIZE(clk_oscout1_parents),
0, fch_data->base + CLKDRVSTR2, OSCOUT1CLK25MHZ, 3, 0,
NULL);
clk_set_parent(hws[ST_CLK_MUX]->clk, hws[ST_CLK_48M]->clk);
hws[ST_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1",
"oscout1_mux", 0, fch_data->base + MISCCLKCNTL1,
OSCCLKENB, CLK_GATE_SET_TO_DISABLE, NULL);
devm_clk_hw_register_clkdev(&pdev->dev, hws[ST_CLK_GATE],
"oscout1", NULL);
} else {
hws[RV_CLK_48M] = clk_hw_register_fixed_rate(NULL, "clk48MHz",
NULL, 0, 48000000);
hws[RV_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1",
"clk48MHz", 0, fch_data->base + MISCCLKCNTL1,
OSCCLKENB, CLK_GATE_SET_TO_DISABLE, NULL);
devm_clk_hw_register_clkdev(&pdev->dev, hws[RV_CLK_GATE],
"oscout1", NULL);
}
return 0;
}
static int fch_clk_remove(struct platform_device *pdev)
{
int i, clks;
struct fch_clk_data *fch_data;
fch_data = dev_get_platdata(&pdev->dev);
clks = fch_data->is_rv ? RV_MAX_CLKS : ST_MAX_CLKS;
for (i = 0; i < clks; i++)
clk_hw_unregister(hws[i]);
return 0;
}
static struct platform_driver fch_clk_driver = {
.driver = {
.name = "clk-fch",
.suppress_bind_attrs = true,
},
.probe = fch_clk_probe,
.remove = fch_clk_remove,
};
builtin_platform_driver(fch_clk_driver);

78
drivers/clk/x86/clk-st.c
View File

@ -1,78 +0,0 @@
// SPDX-License-Identifier: MIT
/*
* clock framework for AMD Stoney based clocks
*
* Copyright 2018 Advanced Micro Devices, Inc.
*/
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/platform_data/clk-st.h>
#include <linux/platform_device.h>
/* Clock Driving Strength 2 register */
#define CLKDRVSTR2 0x28
/* Clock Control 1 register */
#define MISCCLKCNTL1 0x40
/* Auxiliary clock1 enable bit */
#define OSCCLKENB 2
/* 25Mhz auxiliary output clock freq bit */
#define OSCOUT1CLK25MHZ 16
#define ST_CLK_48M 0
#define ST_CLK_25M 1
#define ST_CLK_MUX 2
#define ST_CLK_GATE 3
#define ST_MAX_CLKS 4
static const char * const clk_oscout1_parents[] = { "clk48MHz", "clk25MHz" };
static struct clk_hw *hws[ST_MAX_CLKS];
static int st_clk_probe(struct platform_device *pdev)
{
struct st_clk_data *st_data;
st_data = dev_get_platdata(&pdev->dev);
if (!st_data || !st_data->base)
return -EINVAL;
hws[ST_CLK_48M] = clk_hw_register_fixed_rate(NULL, "clk48MHz", NULL, 0,
48000000);
hws[ST_CLK_25M] = clk_hw_register_fixed_rate(NULL, "clk25MHz", NULL, 0,
25000000);
hws[ST_CLK_MUX] = clk_hw_register_mux(NULL, "oscout1_mux",
clk_oscout1_parents, ARRAY_SIZE(clk_oscout1_parents),
0, st_data->base + CLKDRVSTR2, OSCOUT1CLK25MHZ, 3, 0, NULL);
clk_set_parent(hws[ST_CLK_MUX]->clk, hws[ST_CLK_48M]->clk);
hws[ST_CLK_GATE] = clk_hw_register_gate(NULL, "oscout1", "oscout1_mux",
0, st_data->base + MISCCLKCNTL1, OSCCLKENB,
CLK_GATE_SET_TO_DISABLE, NULL);
devm_clk_hw_register_clkdev(&pdev->dev, hws[ST_CLK_GATE], "oscout1",
NULL);
return 0;
}
static int st_clk_remove(struct platform_device *pdev)
{
int i;
for (i = 0; i < ST_MAX_CLKS; i++)
clk_hw_unregister(hws[i]);
return 0;
}
static struct platform_driver st_clk_driver = {
.driver = {
.name = "clk-st",
.suppress_bind_attrs = true,
},
.probe = st_clk_probe,
.remove = st_clk_remove,
};
builtin_platform_driver(st_clk_driver);

1
drivers/i2c/busses/i2c-designware-platdrv.c
View File

@ -55,6 +55,7 @@ static const struct acpi_device_id dw_i2c_acpi_match[] = {
{ "HISI02A1", 0 },
{ "HISI02A2", 0 },
{ "HISI02A3", 0 },
{ "HYGO0010", ACCESS_INTR_MASK },
{ }
};
MODULE_DEVICE_TABLE(acpi, dw_i2c_acpi_match);

11
include/linux/platform_data/clk-st.h → include/linux/platform_data/clk-fch.h
View File

@ -1,17 +1,18 @@
/* SPDX-License-Identifier: MIT */
/*
* clock framework for AMD Stoney based clock
* clock framework for AMD misc clocks
*
* Copyright 2018 Advanced Micro Devices, Inc.
*/
#ifndef __CLK_ST_H
#define __CLK_ST_H
#ifndef __CLK_FCH_H
#define __CLK_FCH_H
#include <linux/compiler.h>
struct st_clk_data {
struct fch_clk_data {
void __iomem *base;
u32 is_rv;
};
#endif /* __CLK_ST_H */
#endif /* __CLK_FCH_H */