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Renesas ARM Based SoC DT Fixes for v3.18
* Correct IIC0 parent clock on r8a7740 * Correct SD3CKCR address to device tree on r8a7790 -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJUYrybAAoJENfPZGlqN0++V0EP/1VvilCY1UkP4JG142J9GLKl 8V4H30OfVWr9m9O6LPEwOB/qkl9L6mlyu+oxTi1VI+96542IREfYz/REdy3HmgS2 zD7SEMikoqNbuPfjimonBSbtjRvNLrdcNBjrP9u0pJEZYmGBJelNWxTHAsp6fxDy 6nG+/hiNO3i7hyMaZwsYB+5E+9itJkSv4YOS9bh0IAM+WIMN+VasrMSGu9ZKUCT/ f2zcy2xLR/Zmd2ad6zpfFXDznO6C2vBfGg+fZ97K7H5mkSdkpSR5vYwxVWQY+49L iTlevIi9E7ubp3QIgiSDy9qLAmWxL6wGm4Utj90c+jSKeLPd9NTmGAz0bIjVSYND b8pmdww3dbYsxyqsWbYlscpYwxN83jynEQx3ZU0dCEA9X7o7SfkQpZlhw/qkNAIu 3iwEqNbrLLlz9nyl7lMFRUPGcn6pugd5ylq6zhfHR9cRRuMAjkkA/1iTEt4kPXSq 6wFLArgNSID9ood0mpuVzp0xWmqY9XsxwYQJLfIE53W8CatWP/HAWAEBiunCJVTg p0A1WbRrVL0GIQ8QEOjfAo+a0WF0gaiT4Xr66tq6U0o0JwSXr7fws77cl82GXyol m7AKJ+lzPS2RQg0DdjZAQ1OkA9laQmXtQb44a6OipMw2JdM3oG5yvK0IAb+sxjh1 mOiUw0Zggyf/L+PAxeKJ =Du2A -----END PGP SIGNATURE----- Merge tag 'renesas-dt-fixes-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into fixes Pull "Renesas ARM Based SoC DT Fixes for v3.18" from Simon Horman: * Correct IIC0 parent clock on r8a7740 * Correct SD3CKCR address to device tree on r8a7790 * tag 'renesas-dt-fixes-for-v3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: ARM: shmobile: r8a7740 dtsi: Correct IIC0 parent clock ARM: shmobile: r8a7790: Fix SD3CKCR address to device tree Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
commit
3410d4247c
@ -433,7 +433,7 @@
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clocks = <&cpg_clocks R8A7740_CLK_S>,
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<&cpg_clocks R8A7740_CLK_S>, <&sub_clk>,
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<&cpg_clocks R8A7740_CLK_B>,
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<&sub_clk>, <&sub_clk>,
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<&cpg_clocks R8A7740_CLK_HPP>, <&sub_clk>,
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<&cpg_clocks R8A7740_CLK_B>;
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#clock-cells = <1>;
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renesas,clock-indices = <
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@ -666,9 +666,9 @@
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#clock-cells = <0>;
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clock-output-names = "sd2";
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};
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sd3_clk: sd3_clk@e615007c {
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sd3_clk: sd3_clk@e615026c {
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compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
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reg = <0 0xe615007c 0 4>;
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reg = <0 0xe615026c 0 4>;
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clocks = <&pll1_div2_clk>;
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#clock-cells = <0>;
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clock-output-names = "sd3";
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