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locking/barriers: Introduce smp_acquire__after_ctrl_dep()
Introduce smp_acquire__after_ctrl_dep(), this construct is not uncommon, but the lack of this barrier is. Use it to better express smp_rmb() uses in WRITE_ONCE(), the IPC semaphore code and the qspinlock code. Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Andrew Morton <akpm@linux-foundation.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Paul E. McKenney <paulmck@linux.vnet.ibm.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: linux-kernel@vger.kernel.org Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@ -304,6 +304,17 @@ static __always_inline void __write_once_size(volatile void *p, void *res, int s
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__u.__val; \
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})
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/**
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* smp_acquire__after_ctrl_dep() - Provide ACQUIRE ordering after a control dependency
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*
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* A control dependency provides a LOAD->STORE order, the additional RMB
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* provides LOAD->LOAD order, together they provide LOAD->{LOAD,STORE} order,
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* aka. (load)-ACQUIRE.
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*
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* Architectures that do not do load speculation can have this be barrier().
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*/
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#define smp_acquire__after_ctrl_dep() smp_rmb()
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/**
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* smp_cond_load_acquire() - (Spin) wait for cond with ACQUIRE ordering
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* @ptr: pointer to the variable to wait on
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@ -314,10 +325,6 @@ static __always_inline void __write_once_size(volatile void *p, void *res, int s
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*
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* Due to C lacking lambda expressions we load the value of *ptr into a
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* pre-named variable @VAL to be used in @cond.
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*
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* The control dependency provides a LOAD->STORE order, the additional RMB
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* provides LOAD->LOAD order, together they provide LOAD->{LOAD,STORE} order,
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* aka. ACQUIRE.
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*/
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#ifndef smp_cond_load_acquire
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#define smp_cond_load_acquire(ptr, cond_expr) ({ \
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@ -329,7 +336,7 @@ static __always_inline void __write_once_size(volatile void *p, void *res, int s
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break; \
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cpu_relax(); \
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} \
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smp_rmb(); /* ctrl + rmb := acquire */ \
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smp_acquire__after_ctrl_dep(); \
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VAL; \
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})
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#endif
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14
ipc/sem.c
14
ipc/sem.c
@ -259,16 +259,6 @@ static void sem_rcu_free(struct rcu_head *head)
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ipc_rcu_free(head);
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}
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/*
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* spin_unlock_wait() and !spin_is_locked() are not memory barriers, they
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* are only control barriers.
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* The code must pair with spin_unlock(&sem->lock) or
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* spin_unlock(&sem_perm.lock), thus just the control barrier is insufficient.
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*
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* smp_rmb() is sufficient, as writes cannot pass the control barrier.
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*/
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#define ipc_smp_acquire__after_spin_is_unlocked() smp_rmb()
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/*
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* Wait until all currently ongoing simple ops have completed.
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* Caller must own sem_perm.lock.
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@ -292,7 +282,7 @@ static void sem_wait_array(struct sem_array *sma)
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sem = sma->sem_base + i;
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spin_unlock_wait(&sem->lock);
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}
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ipc_smp_acquire__after_spin_is_unlocked();
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smp_acquire__after_ctrl_dep();
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}
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/*
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@ -350,7 +340,7 @@ static inline int sem_lock(struct sem_array *sma, struct sembuf *sops,
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* complex_count++;
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* spin_unlock(sem_perm.lock);
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*/
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ipc_smp_acquire__after_spin_is_unlocked();
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smp_acquire__after_ctrl_dep();
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/*
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* Now repeat the test of complex_count:
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@ -379,7 +379,7 @@ void queued_spin_unlock_wait(struct qspinlock *lock)
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cpu_relax();
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done:
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smp_rmb(); /* CTRL + RMB -> ACQUIRE */
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smp_acquire__after_ctrl_dep();
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}
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EXPORT_SYMBOL(queued_spin_unlock_wait);
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#endif
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