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Merge tag 'zynq-cleanup-for-3.15-v2' of git://git.xilinx.com/linux-xlnx into next/cleanup2
Merge "arm: Xilinx Zynq cleanup patches for v3.15" from Michal Simek: - Redesign SLCR initialization to enable driver developing which targets SLCR space * tag 'zynq-cleanup-for-3.15-v2' of git://git.xilinx.com/linux-xlnx: ARM: zynq: Add waituart implementation ARM: zynq: Move of_clk_init from clock driver ARM: zynq: Introduce zynq_slcr_unlock() ARM: zynq: Add and use zynq_slcr_read/write() helper functions ARM: zynq: Make zynq_slcr_base static ARM: zynq: Map I/O memory on clkc init ARM: zynq: Hang iomapped slcr address on device_node ARM: zynq: Split slcr in two parts ARM: zynq: Move clock_init from slcr to common arm: dt: zynq: Add fclk-enable property to clkc node [Arnd: remove SOC_BUS support from pull request] Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann
commit
32adc19d4b
@ -14,6 +14,7 @@ for all clock consumers of PS clocks.
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Required properties:
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- #clock-cells : Must be 1
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- compatible : "xlnx,ps7-clkc"
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- reg : SLCR offset and size taken via syscon < 0x100 0x100 >
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- ps-clk-frequency : Frequency of the oscillator providing ps_clk in HZ
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(usually 33 MHz oscillators are used for Zynq platforms)
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- clock-output-names : List of strings used to name the clock outputs. Shall be
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@ -87,10 +88,11 @@ Clock outputs:
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47: dbg_apb
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Example:
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clkc: clkc {
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clkc: clkc@100 {
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#clock-cells = <1>;
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compatible = "xlnx,ps7-clkc";
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ps-clk-frequency = <33333333>;
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reg = <0x100 0x100>;
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clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
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"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
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"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
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@ -123,29 +123,28 @@
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} ;
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slcr: slcr@f8000000 {
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compatible = "xlnx,zynq-slcr";
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "xlnx,zynq-slcr", "syscon";
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reg = <0xF8000000 0x1000>;
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clocks {
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#address-cells = <1>;
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#size-cells = <0>;
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clkc: clkc {
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#clock-cells = <1>;
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compatible = "xlnx,ps7-clkc";
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ps-clk-frequency = <33333333>;
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clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
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"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
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"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
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"fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
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"sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
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"dma", "usb0_aper", "usb1_aper", "gem0_aper",
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"gem1_aper", "sdio0_aper", "sdio1_aper",
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"spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
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"i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
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"gpio_aper", "lqspi_aper", "smc_aper", "swdt",
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"dbg_trc", "dbg_apb";
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};
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ranges;
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clkc: clkc@100 {
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#clock-cells = <1>;
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compatible = "xlnx,ps7-clkc";
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ps-clk-frequency = <33333333>;
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fclk-enable = <0>;
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clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
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"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
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"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
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"fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
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"sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
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"dma", "usb0_aper", "usb1_aper", "gem0_aper",
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"gem1_aper", "sdio0_aper", "sdio1_aper",
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"spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
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"i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
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"gpio_aper", "lqspi_aper", "smc_aper", "swdt",
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"dbg_trc", "dbg_apb";
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reg = <0x100 0x100>;
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};
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};
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@ -42,6 +42,9 @@
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.endm
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.macro waituart,rd,rx
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1001: ldr \rd, [\rx, #UART_SR_OFFSET]
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tst \rd, #UART_SR_TXEMPTY
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beq 1001b
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.endm
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.macro busyuart,rd,rx
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@ -14,5 +14,6 @@ config ARCH_ZYNQ
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select SPARSE_IRQ
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select CADENCE_TTC_TIMER
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select ARM_GLOBAL_TIMER
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select MFD_SYSCON
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help
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Support for Xilinx Zynq ARM Cortex A9 Platform
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@ -19,6 +19,7 @@
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#include <linux/cpumask.h>
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#include <linux/platform_device.h>
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#include <linux/clk.h>
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#include <linux/clk-provider.h>
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#include <linux/clk/zynq.h>
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#include <linux/clocksource.h>
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#include <linux/of_address.h>
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@ -72,11 +73,16 @@ static void __init zynq_init_machine(void)
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of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL);
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platform_device_register(&zynq_cpuidle_device);
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zynq_slcr_init();
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}
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static void __init zynq_timer_init(void)
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{
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zynq_slcr_init();
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zynq_early_slcr_init();
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zynq_clock_init();
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of_clk_init(NULL);
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clocksource_of_init();
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}
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@ -20,6 +20,7 @@
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void zynq_secondary_startup(void);
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extern int zynq_slcr_init(void);
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extern int zynq_early_slcr_init(void);
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extern void zynq_slcr_system_reset(void);
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extern void zynq_slcr_cpu_stop(int cpu);
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extern void zynq_slcr_cpu_start(int cpu);
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@ -33,7 +34,6 @@ extern int zynq_cpun_start(u32 address, int cpu);
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extern struct smp_operations zynq_smp_ops __initdata;
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#endif
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extern void __iomem *zynq_slcr_base;
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extern void __iomem *zynq_scu_base;
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/* Hotplug */
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@ -15,7 +15,9 @@
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*/
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#include <linux/io.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of_address.h>
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#include <linux/regmap.h>
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#include <linux/clk/zynq.h>
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#include "common.h"
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@ -29,7 +31,56 @@
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#define SLCR_A9_CPU_CLKSTOP 0x10
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#define SLCR_A9_CPU_RST 0x1
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void __iomem *zynq_slcr_base;
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static void __iomem *zynq_slcr_base;
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static struct regmap *zynq_slcr_regmap;
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/**
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* zynq_slcr_write - Write to a register in SLCR block
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*
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* @val: Value to write to the register
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* @offset: Register offset in SLCR block
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*
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* Return: a negative value on error, 0 on success
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*/
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static int zynq_slcr_write(u32 val, u32 offset)
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{
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if (!zynq_slcr_regmap) {
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writel(val, zynq_slcr_base + offset);
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return 0;
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}
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return regmap_write(zynq_slcr_regmap, offset, val);
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}
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/**
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* zynq_slcr_read - Read a register in SLCR block
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*
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* @val: Pointer to value to be read from SLCR
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* @offset: Register offset in SLCR block
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*
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* Return: a negative value on error, 0 on success
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*/
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static int zynq_slcr_read(u32 *val, u32 offset)
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{
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if (zynq_slcr_regmap)
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return regmap_read(zynq_slcr_regmap, offset, val);
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*val = readl(zynq_slcr_base + offset);
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return 0;
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}
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/**
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* zynq_slcr_unlock - Unlock SLCR registers
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*
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* Return: a negative value on error, 0 on success
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*/
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static inline int zynq_slcr_unlock(void)
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{
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zynq_slcr_write(SLCR_UNLOCK_MAGIC, SLCR_UNLOCK_OFFSET);
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return 0;
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}
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/**
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* zynq_slcr_system_reset - Reset the entire system.
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@ -43,16 +94,16 @@ void zynq_slcr_system_reset(void)
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* Note that this seems to require raw i/o
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* functions or there's a lockup?
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*/
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writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK_OFFSET);
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zynq_slcr_unlock();
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/*
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* Clear 0x0F000000 bits of reboot status register to workaround
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* the FSBL not loading the bitstream after soft-reboot
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* This is a temporary solution until we know more.
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*/
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reboot = readl(zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
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writel(reboot & 0xF0FFFFFF, zynq_slcr_base + SLCR_REBOOT_STATUS_OFFSET);
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writel(1, zynq_slcr_base + SLCR_PS_RST_CTRL_OFFSET);
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zynq_slcr_read(&reboot, SLCR_REBOOT_STATUS_OFFSET);
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zynq_slcr_write(reboot & 0xF0FFFFFF, SLCR_REBOOT_STATUS_OFFSET);
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zynq_slcr_write(1, SLCR_PS_RST_CTRL_OFFSET);
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}
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/**
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@ -61,11 +112,13 @@ void zynq_slcr_system_reset(void)
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*/
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void zynq_slcr_cpu_start(int cpu)
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{
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u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
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u32 reg;
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zynq_slcr_read(®, SLCR_A9_CPU_RST_CTRL_OFFSET);
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reg &= ~(SLCR_A9_CPU_RST << cpu);
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writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
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zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
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reg &= ~(SLCR_A9_CPU_CLKSTOP << cpu);
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writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
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zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
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}
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/**
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@ -74,18 +127,39 @@ void zynq_slcr_cpu_start(int cpu)
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*/
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void zynq_slcr_cpu_stop(int cpu)
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{
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u32 reg = readl(zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
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u32 reg;
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zynq_slcr_read(®, SLCR_A9_CPU_RST_CTRL_OFFSET);
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reg |= (SLCR_A9_CPU_CLKSTOP | SLCR_A9_CPU_RST) << cpu;
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writel(reg, zynq_slcr_base + SLCR_A9_CPU_RST_CTRL_OFFSET);
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zynq_slcr_write(reg, SLCR_A9_CPU_RST_CTRL_OFFSET);
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}
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/**
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* zynq_slcr_init
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* Returns 0 on success, negative errno otherwise.
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* zynq_slcr_init - Regular slcr driver init
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*
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* Return: 0 on success, negative errno otherwise.
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*
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* Called early during boot from platform code to remap SLCR area.
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*/
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int __init zynq_slcr_init(void)
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{
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zynq_slcr_regmap = syscon_regmap_lookup_by_compatible("xlnx,zynq-slcr");
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if (IS_ERR(zynq_slcr_regmap)) {
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pr_err("%s: failed to find zynq-slcr\n", __func__);
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return -ENODEV;
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}
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return 0;
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}
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/**
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* zynq_early_slcr_init - Early slcr init function
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*
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* Return: 0 on success, negative errno otherwise.
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*
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* Called very early during boot from platform code to unlock SLCR.
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*/
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int __init zynq_early_slcr_init(void)
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{
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struct device_node *np;
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@ -101,13 +175,13 @@ int __init zynq_slcr_init(void)
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BUG();
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}
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np->data = (__force void *)zynq_slcr_base;
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/* unlock the SLCR so that registers can be changed */
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writel(SLCR_UNLOCK_MAGIC, zynq_slcr_base + SLCR_UNLOCK_OFFSET);
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zynq_slcr_unlock();
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pr_info("%s mapped to %p\n", np->name, zynq_slcr_base);
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zynq_clock_init(zynq_slcr_base);
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of_node_put(np);
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return 0;
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@ -21,34 +21,35 @@
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#include <linux/clk/zynq.h>
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#include <linux/clk-provider.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/slab.h>
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#include <linux/string.h>
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#include <linux/io.h>
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static void __iomem *zynq_slcr_base_priv;
|
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static void __iomem *zynq_clkc_base;
|
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#define SLCR_ARMPLL_CTRL (zynq_slcr_base_priv + 0x100)
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#define SLCR_DDRPLL_CTRL (zynq_slcr_base_priv + 0x104)
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#define SLCR_IOPLL_CTRL (zynq_slcr_base_priv + 0x108)
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#define SLCR_PLL_STATUS (zynq_slcr_base_priv + 0x10c)
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#define SLCR_ARM_CLK_CTRL (zynq_slcr_base_priv + 0x120)
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#define SLCR_DDR_CLK_CTRL (zynq_slcr_base_priv + 0x124)
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#define SLCR_DCI_CLK_CTRL (zynq_slcr_base_priv + 0x128)
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#define SLCR_APER_CLK_CTRL (zynq_slcr_base_priv + 0x12c)
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#define SLCR_GEM0_CLK_CTRL (zynq_slcr_base_priv + 0x140)
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#define SLCR_GEM1_CLK_CTRL (zynq_slcr_base_priv + 0x144)
|
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#define SLCR_SMC_CLK_CTRL (zynq_slcr_base_priv + 0x148)
|
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#define SLCR_LQSPI_CLK_CTRL (zynq_slcr_base_priv + 0x14c)
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#define SLCR_SDIO_CLK_CTRL (zynq_slcr_base_priv + 0x150)
|
||||
#define SLCR_UART_CLK_CTRL (zynq_slcr_base_priv + 0x154)
|
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#define SLCR_SPI_CLK_CTRL (zynq_slcr_base_priv + 0x158)
|
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#define SLCR_CAN_CLK_CTRL (zynq_slcr_base_priv + 0x15c)
|
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#define SLCR_CAN_MIOCLK_CTRL (zynq_slcr_base_priv + 0x160)
|
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#define SLCR_DBG_CLK_CTRL (zynq_slcr_base_priv + 0x164)
|
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#define SLCR_PCAP_CLK_CTRL (zynq_slcr_base_priv + 0x168)
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#define SLCR_FPGA0_CLK_CTRL (zynq_slcr_base_priv + 0x170)
|
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#define SLCR_621_TRUE (zynq_slcr_base_priv + 0x1c4)
|
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#define SLCR_SWDT_CLK_SEL (zynq_slcr_base_priv + 0x304)
|
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#define SLCR_ARMPLL_CTRL (zynq_clkc_base + 0x00)
|
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#define SLCR_DDRPLL_CTRL (zynq_clkc_base + 0x04)
|
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#define SLCR_IOPLL_CTRL (zynq_clkc_base + 0x08)
|
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#define SLCR_PLL_STATUS (zynq_clkc_base + 0x0c)
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#define SLCR_ARM_CLK_CTRL (zynq_clkc_base + 0x20)
|
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#define SLCR_DDR_CLK_CTRL (zynq_clkc_base + 0x24)
|
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#define SLCR_DCI_CLK_CTRL (zynq_clkc_base + 0x28)
|
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#define SLCR_APER_CLK_CTRL (zynq_clkc_base + 0x2c)
|
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#define SLCR_GEM0_CLK_CTRL (zynq_clkc_base + 0x40)
|
||||
#define SLCR_GEM1_CLK_CTRL (zynq_clkc_base + 0x44)
|
||||
#define SLCR_SMC_CLK_CTRL (zynq_clkc_base + 0x48)
|
||||
#define SLCR_LQSPI_CLK_CTRL (zynq_clkc_base + 0x4c)
|
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#define SLCR_SDIO_CLK_CTRL (zynq_clkc_base + 0x50)
|
||||
#define SLCR_UART_CLK_CTRL (zynq_clkc_base + 0x54)
|
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#define SLCR_SPI_CLK_CTRL (zynq_clkc_base + 0x58)
|
||||
#define SLCR_CAN_CLK_CTRL (zynq_clkc_base + 0x5c)
|
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#define SLCR_CAN_MIOCLK_CTRL (zynq_clkc_base + 0x60)
|
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#define SLCR_DBG_CLK_CTRL (zynq_clkc_base + 0x64)
|
||||
#define SLCR_PCAP_CLK_CTRL (zynq_clkc_base + 0x68)
|
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#define SLCR_FPGA0_CLK_CTRL (zynq_clkc_base + 0x70)
|
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#define SLCR_621_TRUE (zynq_clkc_base + 0xc4)
|
||||
#define SLCR_SWDT_CLK_SEL (zynq_clkc_base + 0x204)
|
||||
|
||||
#define NUM_MIO_PINS 54
|
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|
||||
@ -569,8 +570,42 @@ static void __init zynq_clk_setup(struct device_node *np)
|
||||
|
||||
CLK_OF_DECLARE(zynq_clkc, "xlnx,ps7-clkc", zynq_clk_setup);
|
||||
|
||||
void __init zynq_clock_init(void __iomem *slcr_base)
|
||||
void __init zynq_clock_init(void)
|
||||
{
|
||||
zynq_slcr_base_priv = slcr_base;
|
||||
of_clk_init(NULL);
|
||||
struct device_node *np;
|
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struct device_node *slcr;
|
||||
struct resource res;
|
||||
|
||||
np = of_find_compatible_node(NULL, NULL, "xlnx,ps7-clkc");
|
||||
if (!np) {
|
||||
pr_err("%s: clkc node not found\n", __func__);
|
||||
goto np_err;
|
||||
}
|
||||
|
||||
if (of_address_to_resource(np, 0, &res)) {
|
||||
pr_err("%s: failed to get resource\n", np->name);
|
||||
goto np_err;
|
||||
}
|
||||
|
||||
slcr = of_get_parent(np);
|
||||
|
||||
if (slcr->data) {
|
||||
zynq_clkc_base = (__force void __iomem *)slcr->data + res.start;
|
||||
} else {
|
||||
pr_err("%s: Unable to get I/O memory\n", np->name);
|
||||
of_node_put(slcr);
|
||||
goto np_err;
|
||||
}
|
||||
|
||||
pr_info("%s: clkc starts at %p\n", __func__, zynq_clkc_base);
|
||||
|
||||
of_node_put(slcr);
|
||||
of_node_put(np);
|
||||
|
||||
return;
|
||||
|
||||
np_err:
|
||||
of_node_put(np);
|
||||
BUG();
|
||||
return;
|
||||
}
|
||||
|
||||
@ -22,7 +22,7 @@
|
||||
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
void zynq_clock_init(void __iomem *slcr);
|
||||
void zynq_clock_init(void);
|
||||
|
||||
struct clk *clk_register_zynq_pll(const char *name, const char *parent,
|
||||
void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user