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pmdomain: amlogic: remove obsolete vpu domain driver
meson-gx-pwrc-vpu has been superseded by meson-ee-pwrc since
commit 53773f2dfd ("soc: amlogic: meson-ee-pwrc: add support for the Meson GX SoCs"),
so v5.8.
This driver is obsolete and no longer used or tested.
There is no reason to keep it around so remove it.
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20240730130227.712894-1-jbrunet@baylibre.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
This commit is contained in:
Jerome Brunet
Ulf Hansson
parent
de9c2c66ad
commit
328fc9b298
@ -1,17 +1,6 @@
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# SPDX-License-Identifier: GPL-2.0-only
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menu "Amlogic PM Domains"
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config MESON_GX_PM_DOMAINS
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tristate "Amlogic Meson GX Power Domains driver"
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depends on ARCH_MESON || COMPILE_TEST
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depends on PM && OF
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default ARCH_MESON
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select PM_GENERIC_DOMAINS
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select PM_GENERIC_DOMAINS_OF
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help
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Say yes to expose Amlogic Meson GX Power Domains as
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Generic Power Domains.
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config MESON_EE_PM_DOMAINS
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tristate "Amlogic Meson Everything-Else Power Domains driver"
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depends on ARCH_MESON || COMPILE_TEST
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@ -1,4 +1,3 @@
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# SPDX-License-Identifier: GPL-2.0-only
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obj-$(CONFIG_MESON_GX_PM_DOMAINS) += meson-gx-pwrc-vpu.o
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obj-$(CONFIG_MESON_EE_PM_DOMAINS) += meson-ee-pwrc.o
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obj-$(CONFIG_MESON_SECURE_PM_DOMAINS) += meson-secure-pwrc.o
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@ -1,380 +0,0 @@
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/*
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* Copyright (c) 2017 BayLibre, SAS
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* Author: Neil Armstrong <narmstrong@baylibre.com>
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*
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* SPDX-License-Identifier: GPL-2.0+
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*/
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#include <linux/platform_device.h>
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#include <linux/pm_domain.h>
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#include <linux/bitfield.h>
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#include <linux/regmap.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of.h>
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#include <linux/reset.h>
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#include <linux/clk.h>
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#include <linux/module.h>
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/* AO Offsets */
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#define AO_RTI_GEN_PWR_SLEEP0 (0x3a << 2)
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#define GEN_PWR_VPU_HDMI BIT(8)
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#define GEN_PWR_VPU_HDMI_ISO BIT(9)
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/* HHI Offsets */
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#define HHI_MEM_PD_REG0 (0x40 << 2)
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#define HHI_VPU_MEM_PD_REG0 (0x41 << 2)
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#define HHI_VPU_MEM_PD_REG1 (0x42 << 2)
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#define HHI_VPU_MEM_PD_REG2 (0x4d << 2)
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struct meson_gx_pwrc_vpu {
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struct generic_pm_domain genpd;
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struct regmap *regmap_ao;
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struct regmap *regmap_hhi;
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struct reset_control *rstc;
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struct clk *vpu_clk;
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struct clk *vapb_clk;
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};
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static inline
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struct meson_gx_pwrc_vpu *genpd_to_pd(struct generic_pm_domain *d)
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{
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return container_of(d, struct meson_gx_pwrc_vpu, genpd);
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}
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static int meson_gx_pwrc_vpu_power_off(struct generic_pm_domain *genpd)
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{
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struct meson_gx_pwrc_vpu *pd = genpd_to_pd(genpd);
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int i;
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regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
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GEN_PWR_VPU_HDMI_ISO, GEN_PWR_VPU_HDMI_ISO);
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udelay(20);
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/* Power Down Memories */
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for (i = 0; i < 32; i += 2) {
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regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0,
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0x3 << i, 0x3 << i);
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udelay(5);
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}
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for (i = 0; i < 32; i += 2) {
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regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1,
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0x3 << i, 0x3 << i);
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udelay(5);
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}
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for (i = 8; i < 16; i++) {
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regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0,
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BIT(i), BIT(i));
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udelay(5);
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}
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udelay(20);
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regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
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GEN_PWR_VPU_HDMI, GEN_PWR_VPU_HDMI);
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msleep(20);
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clk_disable_unprepare(pd->vpu_clk);
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clk_disable_unprepare(pd->vapb_clk);
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return 0;
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}
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static int meson_g12a_pwrc_vpu_power_off(struct generic_pm_domain *genpd)
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{
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struct meson_gx_pwrc_vpu *pd = genpd_to_pd(genpd);
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int i;
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regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
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GEN_PWR_VPU_HDMI_ISO, GEN_PWR_VPU_HDMI_ISO);
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udelay(20);
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/* Power Down Memories */
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for (i = 0; i < 32; i += 2) {
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regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0,
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0x3 << i, 0x3 << i);
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udelay(5);
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}
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for (i = 0; i < 32; i += 2) {
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regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1,
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0x3 << i, 0x3 << i);
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udelay(5);
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}
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for (i = 0; i < 32; i += 2) {
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regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG2,
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0x3 << i, 0x3 << i);
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udelay(5);
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}
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for (i = 8; i < 16; i++) {
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regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0,
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BIT(i), BIT(i));
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udelay(5);
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}
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udelay(20);
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regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
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GEN_PWR_VPU_HDMI, GEN_PWR_VPU_HDMI);
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msleep(20);
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clk_disable_unprepare(pd->vpu_clk);
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clk_disable_unprepare(pd->vapb_clk);
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return 0;
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}
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static int meson_gx_pwrc_vpu_setup_clk(struct meson_gx_pwrc_vpu *pd)
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{
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int ret;
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ret = clk_prepare_enable(pd->vpu_clk);
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if (ret)
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return ret;
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ret = clk_prepare_enable(pd->vapb_clk);
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if (ret)
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clk_disable_unprepare(pd->vpu_clk);
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return ret;
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}
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static int meson_gx_pwrc_vpu_power_on(struct generic_pm_domain *genpd)
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{
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struct meson_gx_pwrc_vpu *pd = genpd_to_pd(genpd);
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int ret;
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int i;
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regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
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GEN_PWR_VPU_HDMI, 0);
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udelay(20);
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/* Power Up Memories */
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for (i = 0; i < 32; i += 2) {
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regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0,
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0x3 << i, 0);
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udelay(5);
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}
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for (i = 0; i < 32; i += 2) {
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regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1,
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0x3 << i, 0);
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udelay(5);
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}
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for (i = 8; i < 16; i++) {
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regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0,
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BIT(i), 0);
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udelay(5);
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}
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udelay(20);
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ret = reset_control_assert(pd->rstc);
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if (ret)
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return ret;
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regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
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GEN_PWR_VPU_HDMI_ISO, 0);
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ret = reset_control_deassert(pd->rstc);
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if (ret)
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return ret;
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ret = meson_gx_pwrc_vpu_setup_clk(pd);
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if (ret)
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return ret;
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return 0;
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}
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static int meson_g12a_pwrc_vpu_power_on(struct generic_pm_domain *genpd)
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{
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struct meson_gx_pwrc_vpu *pd = genpd_to_pd(genpd);
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int ret;
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int i;
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regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
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GEN_PWR_VPU_HDMI, 0);
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udelay(20);
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/* Power Up Memories */
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for (i = 0; i < 32; i += 2) {
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regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG0,
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0x3 << i, 0);
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udelay(5);
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}
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for (i = 0; i < 32; i += 2) {
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regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG1,
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0x3 << i, 0);
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udelay(5);
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}
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for (i = 0; i < 32; i += 2) {
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regmap_update_bits(pd->regmap_hhi, HHI_VPU_MEM_PD_REG2,
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0x3 << i, 0);
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udelay(5);
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}
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for (i = 8; i < 16; i++) {
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regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0,
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BIT(i), 0);
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udelay(5);
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}
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udelay(20);
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ret = reset_control_assert(pd->rstc);
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if (ret)
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return ret;
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regmap_update_bits(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0,
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GEN_PWR_VPU_HDMI_ISO, 0);
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ret = reset_control_deassert(pd->rstc);
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if (ret)
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return ret;
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ret = meson_gx_pwrc_vpu_setup_clk(pd);
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if (ret)
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return ret;
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return 0;
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}
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static bool meson_gx_pwrc_vpu_get_power(struct meson_gx_pwrc_vpu *pd)
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{
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u32 reg;
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regmap_read(pd->regmap_ao, AO_RTI_GEN_PWR_SLEEP0, ®);
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return (reg & GEN_PWR_VPU_HDMI);
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}
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static struct meson_gx_pwrc_vpu vpu_hdmi_pd = {
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.genpd = {
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.name = "vpu_hdmi",
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.power_off = meson_gx_pwrc_vpu_power_off,
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.power_on = meson_gx_pwrc_vpu_power_on,
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},
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};
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static struct meson_gx_pwrc_vpu vpu_hdmi_pd_g12a = {
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.genpd = {
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.name = "vpu_hdmi",
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.power_off = meson_g12a_pwrc_vpu_power_off,
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.power_on = meson_g12a_pwrc_vpu_power_on,
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},
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};
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static int meson_gx_pwrc_vpu_probe(struct platform_device *pdev)
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{
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const struct meson_gx_pwrc_vpu *vpu_pd_match;
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struct regmap *regmap_ao, *regmap_hhi;
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struct meson_gx_pwrc_vpu *vpu_pd;
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struct device_node *parent_np;
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struct reset_control *rstc;
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struct clk *vpu_clk;
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struct clk *vapb_clk;
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bool powered_off;
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int ret;
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vpu_pd_match = of_device_get_match_data(&pdev->dev);
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if (!vpu_pd_match) {
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dev_err(&pdev->dev, "failed to get match data\n");
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return -ENODEV;
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}
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vpu_pd = devm_kzalloc(&pdev->dev, sizeof(*vpu_pd), GFP_KERNEL);
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if (!vpu_pd)
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return -ENOMEM;
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memcpy(vpu_pd, vpu_pd_match, sizeof(*vpu_pd));
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parent_np = of_get_parent(pdev->dev.of_node);
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regmap_ao = syscon_node_to_regmap(parent_np);
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of_node_put(parent_np);
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if (IS_ERR(regmap_ao)) {
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dev_err(&pdev->dev, "failed to get regmap\n");
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return PTR_ERR(regmap_ao);
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}
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regmap_hhi = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
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"amlogic,hhi-sysctrl");
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if (IS_ERR(regmap_hhi)) {
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dev_err(&pdev->dev, "failed to get HHI regmap\n");
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return PTR_ERR(regmap_hhi);
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}
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rstc = devm_reset_control_array_get_exclusive(&pdev->dev);
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if (IS_ERR(rstc))
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return dev_err_probe(&pdev->dev, PTR_ERR(rstc),
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"failed to get reset lines\n");
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vpu_clk = devm_clk_get(&pdev->dev, "vpu");
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if (IS_ERR(vpu_clk)) {
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dev_err(&pdev->dev, "vpu clock request failed\n");
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return PTR_ERR(vpu_clk);
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}
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vapb_clk = devm_clk_get(&pdev->dev, "vapb");
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if (IS_ERR(vapb_clk)) {
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dev_err(&pdev->dev, "vapb clock request failed\n");
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return PTR_ERR(vapb_clk);
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}
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vpu_pd->regmap_ao = regmap_ao;
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vpu_pd->regmap_hhi = regmap_hhi;
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vpu_pd->rstc = rstc;
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vpu_pd->vpu_clk = vpu_clk;
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vpu_pd->vapb_clk = vapb_clk;
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platform_set_drvdata(pdev, vpu_pd);
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powered_off = meson_gx_pwrc_vpu_get_power(vpu_pd);
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/* If already powered, sync the clock states */
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if (!powered_off) {
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ret = meson_gx_pwrc_vpu_setup_clk(vpu_pd);
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if (ret)
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return ret;
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}
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vpu_pd->genpd.flags = GENPD_FLAG_ALWAYS_ON;
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pm_genpd_init(&vpu_pd->genpd, NULL, powered_off);
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return of_genpd_add_provider_simple(pdev->dev.of_node,
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&vpu_pd->genpd);
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}
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static void meson_gx_pwrc_vpu_shutdown(struct platform_device *pdev)
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{
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struct meson_gx_pwrc_vpu *vpu_pd = platform_get_drvdata(pdev);
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bool powered_off;
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powered_off = meson_gx_pwrc_vpu_get_power(vpu_pd);
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if (!powered_off)
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vpu_pd->genpd.power_off(&vpu_pd->genpd);
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}
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static const struct of_device_id meson_gx_pwrc_vpu_match_table[] = {
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{ .compatible = "amlogic,meson-gx-pwrc-vpu", .data = &vpu_hdmi_pd },
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{
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.compatible = "amlogic,meson-g12a-pwrc-vpu",
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.data = &vpu_hdmi_pd_g12a
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},
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{ /* sentinel */ }
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};
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MODULE_DEVICE_TABLE(of, meson_gx_pwrc_vpu_match_table);
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static struct platform_driver meson_gx_pwrc_vpu_driver = {
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.probe = meson_gx_pwrc_vpu_probe,
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.shutdown = meson_gx_pwrc_vpu_shutdown,
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.driver = {
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.name = "meson_gx_pwrc_vpu",
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.of_match_table = meson_gx_pwrc_vpu_match_table,
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},
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};
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module_platform_driver(meson_gx_pwrc_vpu_driver);
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MODULE_DESCRIPTION("Amlogic Meson GX Power Domains driver");
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MODULE_LICENSE("GPL v2");
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