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usb:hsotg:samsung: Extract core initialization function
The s3c_hsotg_core_init function has been added to exclude code responsible for Samsung's SoCs USB core initialization. Signed-off-by: Lukasz Majewski <l.majewski@samsung.com> Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com> Signed-off-by: Felipe Balbi <balbi@ti.com>
This commit is contained in:
Lukasz Majewski
Felipe Balbi
parent
d3ca0259c5
commit
308d734e9e
@ -2138,6 +2138,178 @@ static struct s3c_hsotg *our_hsotg;
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S3C_GINTSTS_PTxFEmp | \
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S3C_GINTSTS_RxFLvl)
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/**
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* s3c_hsotg_corereset - issue softreset to the core
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* @hsotg: The device state
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*
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* Issue a soft reset to the core, and await the core finishing it.
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*/
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static int s3c_hsotg_corereset(struct s3c_hsotg *hsotg)
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{
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int timeout;
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u32 grstctl;
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dev_dbg(hsotg->dev, "resetting core\n");
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/* issue soft reset */
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writel(S3C_GRSTCTL_CSftRst, hsotg->regs + S3C_GRSTCTL);
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timeout = 1000;
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do {
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grstctl = readl(hsotg->regs + S3C_GRSTCTL);
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} while ((grstctl & S3C_GRSTCTL_CSftRst) && timeout-- > 0);
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if (grstctl & S3C_GRSTCTL_CSftRst) {
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dev_err(hsotg->dev, "Failed to get CSftRst asserted\n");
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return -EINVAL;
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}
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timeout = 1000;
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while (1) {
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u32 grstctl = readl(hsotg->regs + S3C_GRSTCTL);
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if (timeout-- < 0) {
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dev_info(hsotg->dev,
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"%s: reset failed, GRSTCTL=%08x\n",
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__func__, grstctl);
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return -ETIMEDOUT;
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}
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if (!(grstctl & S3C_GRSTCTL_AHBIdle))
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continue;
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break; /* reset done */
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}
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dev_dbg(hsotg->dev, "reset successful\n");
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return 0;
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}
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static void s3c_hsotg_core_init(struct s3c_hsotg *hsotg)
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{
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s3c_hsotg_corereset(hsotg);
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/*
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* we must now enable ep0 ready for host detection and then
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* set configuration.
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*/
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/* set the PLL on, remove the HNP/SRP and set the PHY */
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writel(S3C_GUSBCFG_PHYIf16 | S3C_GUSBCFG_TOutCal(7) |
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(0x5 << 10), hsotg->regs + S3C_GUSBCFG);
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s3c_hsotg_init_fifo(hsotg);
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__orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
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writel(1 << 18 | S3C_DCFG_DevSpd_HS, hsotg->regs + S3C_DCFG);
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/* Clear any pending OTG interrupts */
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writel(0xffffffff, hsotg->regs + S3C_GOTGINT);
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/* Clear any pending interrupts */
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writel(0xffffffff, hsotg->regs + S3C_GINTSTS);
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writel(S3C_GINTSTS_DisconnInt | S3C_GINTSTS_SessReqInt |
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S3C_GINTSTS_GOUTNakEff | S3C_GINTSTS_GINNakEff |
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S3C_GINTSTS_ConIDStsChng | S3C_GINTSTS_USBRst |
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S3C_GINTSTS_EnumDone | S3C_GINTSTS_OTGInt |
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S3C_GINTSTS_USBSusp | S3C_GINTSTS_WkUpInt |
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S3C_GINTSTS_ErlySusp,
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hsotg->regs + S3C_GINTMSK);
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if (using_dma(hsotg))
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writel(S3C_GAHBCFG_GlblIntrEn | S3C_GAHBCFG_DMAEn |
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S3C_GAHBCFG_HBstLen_Incr4,
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hsotg->regs + S3C_GAHBCFG);
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else
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writel(S3C_GAHBCFG_GlblIntrEn, hsotg->regs + S3C_GAHBCFG);
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/*
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* Enabling INTknTXFEmpMsk here seems to be a big mistake, we end
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* up being flooded with interrupts if the host is polling the
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* endpoint to try and read data.
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*/
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writel(((hsotg->dedicated_fifos) ? S3C_DIEPMSK_TxFIFOEmpty : 0) |
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S3C_DIEPMSK_EPDisbldMsk | S3C_DIEPMSK_XferComplMsk |
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S3C_DIEPMSK_TimeOUTMsk | S3C_DIEPMSK_AHBErrMsk |
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S3C_DIEPMSK_INTknEPMisMsk,
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hsotg->regs + S3C_DIEPMSK);
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/*
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* don't need XferCompl, we get that from RXFIFO in slave mode. In
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* DMA mode we may need this.
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*/
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writel((using_dma(hsotg) ? (S3C_DIEPMSK_XferComplMsk |
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S3C_DIEPMSK_TimeOUTMsk) : 0) |
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S3C_DOEPMSK_EPDisbldMsk | S3C_DOEPMSK_AHBErrMsk |
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S3C_DOEPMSK_SetupMsk,
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hsotg->regs + S3C_DOEPMSK);
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writel(0, hsotg->regs + S3C_DAINTMSK);
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dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
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readl(hsotg->regs + S3C_DIEPCTL0),
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readl(hsotg->regs + S3C_DOEPCTL0));
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/* enable in and out endpoint interrupts */
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s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt);
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/*
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* Enable the RXFIFO when in slave mode, as this is how we collect
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* the data. In DMA mode, we get events from the FIFO but also
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* things we cannot process, so do not use it.
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*/
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if (!using_dma(hsotg))
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s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_RxFLvl);
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/* Enable interrupts for EP0 in and out */
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s3c_hsotg_ctrl_epint(hsotg, 0, 0, 1);
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s3c_hsotg_ctrl_epint(hsotg, 0, 1, 1);
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__orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_PWROnPrgDone);
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udelay(10); /* see openiboot */
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__bic32(hsotg->regs + S3C_DCTL, S3C_DCTL_PWROnPrgDone);
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dev_dbg(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + S3C_DCTL));
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/*
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* S3C_DxEPCTL_USBActEp says RO in manual, but seems to be set by
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* writing to the EPCTL register..
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*/
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/* set to read 1 8byte packet */
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writel(S3C_DxEPTSIZ_MC(1) | S3C_DxEPTSIZ_PktCnt(1) |
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S3C_DxEPTSIZ_XferSize(8), hsotg->regs + DOEPTSIZ0);
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writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
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S3C_DxEPCTL_CNAK | S3C_DxEPCTL_EPEna |
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S3C_DxEPCTL_USBActEp,
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hsotg->regs + S3C_DOEPCTL0);
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/* enable, but don't activate EP0in */
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writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
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S3C_DxEPCTL_USBActEp, hsotg->regs + S3C_DIEPCTL0);
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s3c_hsotg_enqueue_setup(hsotg);
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dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
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readl(hsotg->regs + S3C_DIEPCTL0),
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readl(hsotg->regs + S3C_DOEPCTL0));
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/* clear global NAKs */
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writel(S3C_DCTL_CGOUTNak | S3C_DCTL_CGNPInNAK,
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hsotg->regs + S3C_DCTL);
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/* must be at-least 3ms to allow bus to see disconnect */
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mdelay(3);
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/* remove the soft-disconnect and let's go */
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__bic32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
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}
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/**
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* s3c_hsotg_irq - handle device interrupt
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* @irq: The IRQ number triggered
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@ -2578,54 +2750,6 @@ static struct usb_ep_ops s3c_hsotg_ep_ops = {
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/* note, don't believe we have any call for the fifo routines */
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};
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/**
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* s3c_hsotg_corereset - issue softreset to the core
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* @hsotg: The device state
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*
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* Issue a soft reset to the core, and await the core finishing it.
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*/
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static int s3c_hsotg_corereset(struct s3c_hsotg *hsotg)
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{
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int timeout;
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u32 grstctl;
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dev_dbg(hsotg->dev, "resetting core\n");
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/* issue soft reset */
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writel(S3C_GRSTCTL_CSftRst, hsotg->regs + S3C_GRSTCTL);
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timeout = 1000;
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do {
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grstctl = readl(hsotg->regs + S3C_GRSTCTL);
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} while ((grstctl & S3C_GRSTCTL_CSftRst) && timeout-- > 0);
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if (grstctl & S3C_GRSTCTL_CSftRst) {
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dev_err(hsotg->dev, "Failed to get CSftRst asserted\n");
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return -EINVAL;
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}
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timeout = 1000;
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while (1) {
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u32 grstctl = readl(hsotg->regs + S3C_GRSTCTL);
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if (timeout-- < 0) {
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dev_info(hsotg->dev,
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"%s: reset failed, GRSTCTL=%08x\n",
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__func__, grstctl);
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return -ETIMEDOUT;
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}
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if (!(grstctl & S3C_GRSTCTL_AHBIdle))
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continue;
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break; /* reset done */
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}
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dev_dbg(hsotg->dev, "reset successful\n");
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return 0;
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}
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/**
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* s3c_hsotg_phy_enable - enable platform phy dev
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*
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@ -2706,119 +2830,7 @@ static int s3c_hsotg_start(struct usb_gadget_driver *driver,
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goto err;
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}
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/* we must now enable ep0 ready for host detection and then
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* set configuration. */
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s3c_hsotg_corereset(hsotg);
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/* set the PLL on, remove the HNP/SRP and set the PHY */
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writel(S3C_GUSBCFG_PHYIf16 | S3C_GUSBCFG_TOutCal(7) |
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(0x5 << 10), hsotg->regs + S3C_GUSBCFG);
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/* looks like soft-reset changes state of FIFOs */
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s3c_hsotg_init_fifo(hsotg);
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__orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
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writel(1 << 18 | S3C_DCFG_DevSpd_HS, hsotg->regs + S3C_DCFG);
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/* Clear any pending OTG interrupts */
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writel(0xffffffff, hsotg->regs + S3C_GOTGINT);
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/* Clear any pending interrupts */
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writel(0xffffffff, hsotg->regs + S3C_GINTSTS);
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writel(S3C_GINTSTS_DisconnInt | S3C_GINTSTS_SessReqInt |
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S3C_GINTSTS_ConIDStsChng | S3C_GINTSTS_USBRst |
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S3C_GINTSTS_EnumDone | S3C_GINTSTS_OTGInt |
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S3C_GINTSTS_USBSusp | S3C_GINTSTS_WkUpInt |
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S3C_GINTSTS_GOUTNakEff | S3C_GINTSTS_GINNakEff |
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S3C_GINTSTS_ErlySusp,
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hsotg->regs + S3C_GINTMSK);
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if (using_dma(hsotg))
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writel(S3C_GAHBCFG_GlblIntrEn | S3C_GAHBCFG_DMAEn |
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S3C_GAHBCFG_HBstLen_Incr4,
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hsotg->regs + S3C_GAHBCFG);
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else
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writel(S3C_GAHBCFG_GlblIntrEn, hsotg->regs + S3C_GAHBCFG);
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/* Enabling INTknTXFEmpMsk here seems to be a big mistake, we end
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* up being flooded with interrupts if the host is polling the
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* endpoint to try and read data. */
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writel(S3C_DIEPMSK_TimeOUTMsk | S3C_DIEPMSK_AHBErrMsk |
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S3C_DIEPMSK_INTknEPMisMsk |
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S3C_DIEPMSK_EPDisbldMsk | S3C_DIEPMSK_XferComplMsk |
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((hsotg->dedicated_fifos) ? S3C_DIEPMSK_TxFIFOEmpty : 0),
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hsotg->regs + S3C_DIEPMSK);
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/* don't need XferCompl, we get that from RXFIFO in slave mode. In
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* DMA mode we may need this. */
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writel(S3C_DOEPMSK_SetupMsk | S3C_DOEPMSK_AHBErrMsk |
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S3C_DOEPMSK_EPDisbldMsk |
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(using_dma(hsotg) ? (S3C_DIEPMSK_XferComplMsk |
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S3C_DIEPMSK_TimeOUTMsk) : 0),
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hsotg->regs + S3C_DOEPMSK);
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writel(0, hsotg->regs + S3C_DAINTMSK);
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dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
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readl(hsotg->regs + S3C_DIEPCTL0),
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readl(hsotg->regs + S3C_DOEPCTL0));
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/* enable in and out endpoint interrupts */
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s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_OEPInt | S3C_GINTSTS_IEPInt);
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/* Enable the RXFIFO when in slave mode, as this is how we collect
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* the data. In DMA mode, we get events from the FIFO but also
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* things we cannot process, so do not use it. */
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if (!using_dma(hsotg))
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s3c_hsotg_en_gsint(hsotg, S3C_GINTSTS_RxFLvl);
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/* Enable interrupts for EP0 in and out */
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s3c_hsotg_ctrl_epint(hsotg, 0, 0, 1);
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s3c_hsotg_ctrl_epint(hsotg, 0, 1, 1);
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__orr32(hsotg->regs + S3C_DCTL, S3C_DCTL_PWROnPrgDone);
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udelay(10); /* see openiboot */
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__bic32(hsotg->regs + S3C_DCTL, S3C_DCTL_PWROnPrgDone);
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dev_dbg(hsotg->dev, "DCTL=0x%08x\n", readl(hsotg->regs + S3C_DCTL));
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/* S3C_DxEPCTL_USBActEp says RO in manual, but seems to be set by
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writing to the EPCTL register.. */
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/* set to read 1 8byte packet */
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writel(S3C_DxEPTSIZ_MC(1) | S3C_DxEPTSIZ_PktCnt(1) |
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S3C_DxEPTSIZ_XferSize(8), hsotg->regs + DOEPTSIZ0);
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writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
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S3C_DxEPCTL_CNAK | S3C_DxEPCTL_EPEna |
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S3C_DxEPCTL_USBActEp,
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hsotg->regs + S3C_DOEPCTL0);
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/* enable, but don't activate EP0in */
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writel(s3c_hsotg_ep0_mps(hsotg->eps[0].ep.maxpacket) |
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S3C_DxEPCTL_USBActEp, hsotg->regs + S3C_DIEPCTL0);
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s3c_hsotg_enqueue_setup(hsotg);
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dev_dbg(hsotg->dev, "EP0: DIEPCTL0=0x%08x, DOEPCTL0=0x%08x\n",
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readl(hsotg->regs + S3C_DIEPCTL0),
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readl(hsotg->regs + S3C_DOEPCTL0));
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/* clear global NAKs */
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writel(S3C_DCTL_CGOUTNak | S3C_DCTL_CGNPInNAK,
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hsotg->regs + S3C_DCTL);
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/* must be at-least 3ms to allow bus to see disconnect */
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msleep(3);
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/* remove the soft-disconnect and let's go */
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__bic32(hsotg->regs + S3C_DCTL, S3C_DCTL_SftDiscon);
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/* report to the user, and return */
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s3c_hsotg_core_init(hsotg);
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dev_info(hsotg->dev, "bound driver %s\n", driver->driver.name);
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return 0;
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