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drm/amd/powerplay: add header file for tonga smu and dpm

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These headers provide the SMU interface used by the driver.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: yanyang1 <young.yang@amd.com>
This commit is contained in:
yanyang1 2015-08-17 14:15:20 +08:00 committed by Alex Deucher
parent 7ff1d70a40
commit 306d8db3e7
4 changed files with 1844 additions and 198 deletions
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198
drivers/gpu/drm/amd/amdgpu/tonga_ppsmc.h
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/*
* Copyright 2014 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef TONGA_PP_SMC_H
#define TONGA_PP_SMC_H
#pragma pack(push, 1)
#define PPSMC_SWSTATE_FLAG_DC 0x01
#define PPSMC_SWSTATE_FLAG_UVD 0x02
#define PPSMC_SWSTATE_FLAG_VCE 0x04
#define PPSMC_SWSTATE_FLAG_PCIE_X1 0x08
#define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
#define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
#define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
#define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
#define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
#define PPSMC_SYSTEMFLAG_GDDR5 0x04
#define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP 0x08
#define PPSMC_SYSTEMFLAG_REGULATOR_HOT 0x10
#define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG 0x20
#define PPSMC_SYSTEMFLAG_12CHANNEL 0x40
#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK 0x07
#define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK 0x08
#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE 0x00
#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE 0x01
#define PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH 0x10
#define PPSMC_EXTRAFLAGS_DRIVER_TO_GPIO17 0x20
#define PPSMC_EXTRAFLAGS_PCC_TO_GPIO17 0x40
#define PPSMC_DPM2FLAGS_TDPCLMP 0x01
#define PPSMC_DPM2FLAGS_PWRSHFT 0x02
#define PPSMC_DPM2FLAGS_OCP 0x04
#define PPSMC_DISPLAY_WATERMARK_LOW 0
#define PPSMC_DISPLAY_WATERMARK_HIGH 1
#define PPSMC_STATEFLAG_AUTO_PULSE_SKIP 0x01
#define PPSMC_STATEFLAG_POWERBOOST 0x02
#define PPSMC_STATEFLAG_PSKIP_ON_TDP_FAULT 0x04
#define PPSMC_STATEFLAG_POWERSHIFT 0x08
#define PPSMC_STATEFLAG_SLOW_READ_MARGIN 0x10
#define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 0x20
#define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS 0x40
#define FDO_MODE_HARDWARE 0
#define FDO_MODE_PIECE_WISE_LINEAR 1
enum FAN_CONTROL {
FAN_CONTROL_FUZZY,
FAN_CONTROL_TABLE
};
#define PPSMC_Result_OK ((uint16_t)0x01)
#define PPSMC_Result_NoMore ((uint16_t)0x02)
#define PPSMC_Result_NotNow ((uint16_t)0x03)
#define PPSMC_Result_Failed ((uint16_t)0xFF)
#define PPSMC_Result_UnknownCmd ((uint16_t)0xFE)
#define PPSMC_Result_UnknownVT ((uint16_t)0xFD)
typedef uint16_t PPSMC_Result;
#define PPSMC_isERROR(x) ((uint16_t)0x80 & (x))
#define PPSMC_MSG_Halt ((uint16_t)0x10)
#define PPSMC_MSG_Resume ((uint16_t)0x11)
#define PPSMC_MSG_EnableDPMLevel ((uint16_t)0x12)
#define PPSMC_MSG_ZeroLevelsDisabled ((uint16_t)0x13)
#define PPSMC_MSG_OneLevelsDisabled ((uint16_t)0x14)
#define PPSMC_MSG_TwoLevelsDisabled ((uint16_t)0x15)
#define PPSMC_MSG_EnableThermalInterrupt ((uint16_t)0x16)
#define PPSMC_MSG_RunningOnAC ((uint16_t)0x17)
#define PPSMC_MSG_LevelUp ((uint16_t)0x18)
#define PPSMC_MSG_LevelDown ((uint16_t)0x19)
#define PPSMC_MSG_ResetDPMCounters ((uint16_t)0x1a)
#define PPSMC_MSG_SwitchToSwState ((uint16_t)0x20)
#define PPSMC_MSG_SwitchToSwStateLast ((uint16_t)0x3f)
#define PPSMC_MSG_SwitchToInitialState ((uint16_t)0x40)
#define PPSMC_MSG_NoForcedLevel ((uint16_t)0x41)
#define PPSMC_MSG_ForceHigh ((uint16_t)0x42)
#define PPSMC_MSG_ForceMediumOrHigh ((uint16_t)0x43)
#define PPSMC_MSG_SwitchToMinimumPower ((uint16_t)0x51)
#define PPSMC_MSG_ResumeFromMinimumPower ((uint16_t)0x52)
#define PPSMC_MSG_EnableCac ((uint16_t)0x53)
#define PPSMC_MSG_DisableCac ((uint16_t)0x54)
#define PPSMC_DPMStateHistoryStart ((uint16_t)0x55)
#define PPSMC_DPMStateHistoryStop ((uint16_t)0x56)
#define PPSMC_CACHistoryStart ((uint16_t)0x57)
#define PPSMC_CACHistoryStop ((uint16_t)0x58)
#define PPSMC_TDPClampingActive ((uint16_t)0x59)
#define PPSMC_TDPClampingInactive ((uint16_t)0x5A)
#define PPSMC_StartFanControl ((uint16_t)0x5B)
#define PPSMC_StopFanControl ((uint16_t)0x5C)
#define PPSMC_NoDisplay ((uint16_t)0x5D)
#define PPSMC_HasDisplay ((uint16_t)0x5E)
#define PPSMC_MSG_UVDPowerOFF ((uint16_t)0x60)
#define PPSMC_MSG_UVDPowerON ((uint16_t)0x61)
#define PPSMC_MSG_EnableULV ((uint16_t)0x62)
#define PPSMC_MSG_DisableULV ((uint16_t)0x63)
#define PPSMC_MSG_EnterULV ((uint16_t)0x64)
#define PPSMC_MSG_ExitULV ((uint16_t)0x65)
#define PPSMC_PowerShiftActive ((uint16_t)0x6A)
#define PPSMC_PowerShiftInactive ((uint16_t)0x6B)
#define PPSMC_OCPActive ((uint16_t)0x6C)
#define PPSMC_OCPInactive ((uint16_t)0x6D)
#define PPSMC_CACLongTermAvgEnable ((uint16_t)0x6E)
#define PPSMC_CACLongTermAvgDisable ((uint16_t)0x6F)
#define PPSMC_MSG_InferredStateSweep_Start ((uint16_t)0x70)
#define PPSMC_MSG_InferredStateSweep_Stop ((uint16_t)0x71)
#define PPSMC_MSG_SwitchToLowestInfState ((uint16_t)0x72)
#define PPSMC_MSG_SwitchToNonInfState ((uint16_t)0x73)
#define PPSMC_MSG_AllStateSweep_Start ((uint16_t)0x74)
#define PPSMC_MSG_AllStateSweep_Stop ((uint16_t)0x75)
#define PPSMC_MSG_SwitchNextLowerInfState ((uint16_t)0x76)
#define PPSMC_MSG_SwitchNextHigherInfState ((uint16_t)0x77)
#define PPSMC_MSG_MclkRetrainingTest ((uint16_t)0x78)
#define PPSMC_MSG_ForceTDPClamping ((uint16_t)0x79)
#define PPSMC_MSG_CollectCAC_PowerCorreln ((uint16_t)0x7A)
#define PPSMC_MSG_CollectCAC_WeightCalib ((uint16_t)0x7B)
#define PPSMC_MSG_CollectCAC_SQonly ((uint16_t)0x7C)
#define PPSMC_MSG_CollectCAC_TemperaturePwr ((uint16_t)0x7D)
#define PPSMC_MSG_ExtremitiesTest_Start ((uint16_t)0x7E)
#define PPSMC_MSG_ExtremitiesTest_Stop ((uint16_t)0x7F)
#define PPSMC_FlushDataCache ((uint16_t)0x80)
#define PPSMC_FlushInstrCache ((uint16_t)0x81)
#define PPSMC_MSG_SetEnabledLevels ((uint16_t)0x82)
#define PPSMC_MSG_SetForcedLevels ((uint16_t)0x83)
#define PPSMC_MSG_ResetToDefaults ((uint16_t)0x84)
#define PPSMC_MSG_SetForcedLevelsAndJump ((uint16_t)0x85)
#define PPSMC_MSG_SetCACHistoryMode ((uint16_t)0x86)
#define PPSMC_MSG_EnableDTE ((uint16_t)0x87)
#define PPSMC_MSG_DisableDTE ((uint16_t)0x88)
#define PPSMC_MSG_SmcSpaceSetAddress ((uint16_t)0x89)
#define PPSMC_MSG_SmcSpaceWriteDWordInc ((uint16_t)0x8A)
#define PPSMC_MSG_SmcSpaceWriteWordInc ((uint16_t)0x8B)
#define PPSMC_MSG_SmcSpaceWriteByteInc ((uint16_t)0x8C)
#define PPSMC_MSG_ChangeNearTDPLimit ((uint16_t)0x90)
#define PPSMC_MSG_ChangeSafePowerLimit ((uint16_t)0x91)
#define PPSMC_MSG_DPMStateSweepStart ((uint16_t)0x92)
#define PPSMC_MSG_DPMStateSweepStop ((uint16_t)0x93)
#define PPSMC_MSG_OVRDDisableSCLKDS ((uint16_t)0x94)
#define PPSMC_MSG_CancelDisableOVRDSCLKDS ((uint16_t)0x95)
#define PPSMC_MSG_ThrottleOVRDSCLKDS ((uint16_t)0x96)
#define PPSMC_MSG_CancelThrottleOVRDSCLKDS ((uint16_t)0x97)
#define PPSMC_MSG_GPIO17 ((uint16_t)0x98)
#define PPSMC_MSG_API_SetSvi2Volt_Vddc ((uint16_t)0x99)
#define PPSMC_MSG_API_SetSvi2Volt_Vddci ((uint16_t)0x9A)
#define PPSMC_MSG_API_SetSvi2Volt_Mvdd ((uint16_t)0x9B)
#define PPSMC_MSG_API_GetSvi2Volt_Vddc ((uint16_t)0x9C)
#define PPSMC_MSG_API_GetSvi2Volt_Vddci ((uint16_t)0x9D)
#define PPSMC_MSG_API_GetSvi2Volt_Mvdd ((uint16_t)0x9E)
#define PPSMC_MSG_BREAK ((uint16_t)0xF8)
#define PPSMC_MSG_Test ((uint16_t)0x100)
#define PPSMC_MSG_DRV_DRAM_ADDR_HI ((uint16_t)0x250)
#define PPSMC_MSG_DRV_DRAM_ADDR_LO ((uint16_t)0x251)
#define PPSMC_MSG_SMU_DRAM_ADDR_HI ((uint16_t)0x252)
#define PPSMC_MSG_SMU_DRAM_ADDR_LO ((uint16_t)0x253)
#define PPSMC_MSG_LoadUcodes ((uint16_t)0x254)
typedef uint16_t PPSMC_Msg;
#define PPSMC_EVENT_STATUS_THERMAL 0x00000001
#define PPSMC_EVENT_STATUS_REGULATORHOT 0x00000002
#define PPSMC_EVENT_STATUS_DC 0x00000004
#define PPSMC_EVENT_STATUS_GPIO17 0x00000008
#pragma pack(pop)
#endif

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drivers/gpu/drm/amd/powerplay/inc/smu72.h Normal file
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#ifndef SMU72_H
#define SMU72_H
#if !defined(SMC_MICROCODE)
#pragma pack(push, 1)
#endif
#define SMU__NUM_SCLK_DPM_STATE 8
#define SMU__NUM_MCLK_DPM_LEVELS 4
#define SMU__NUM_LCLK_DPM_LEVELS 8
#define SMU__NUM_PCIE_DPM_LEVELS 8
enum SID_OPTION {
SID_OPTION_HI,
SID_OPTION_LO,
SID_OPTION_COUNT
};
enum Poly3rdOrderCoeff {
LEAKAGE_TEMPERATURE_SCALAR,
LEAKAGE_VOLTAGE_SCALAR,
DYNAMIC_VOLTAGE_SCALAR,
POLY_3RD_ORDER_COUNT
};
struct SMU7_Poly3rdOrder_Data {
int32_t a;
int32_t b;
int32_t c;
int32_t d;
uint8_t a_shift;
uint8_t b_shift;
uint8_t c_shift;
uint8_t x_shift;
};
typedef struct SMU7_Poly3rdOrder_Data SMU7_Poly3rdOrder_Data;
struct Power_Calculator_Data {
uint16_t NoLoadVoltage;
uint16_t LoadVoltage;
uint16_t Resistance;
uint16_t Temperature;
uint16_t BaseLeakage;
uint16_t LkgTempScalar;
uint16_t LkgVoltScalar;
uint16_t LkgAreaScalar;
uint16_t LkgPower;
uint16_t DynVoltScalar;
uint32_t Cac;
uint32_t DynPower;
uint32_t TotalCurrent;
uint32_t TotalPower;
};
typedef struct Power_Calculator_Data PowerCalculatorData_t;
struct Gc_Cac_Weight_Data {
uint8_t index;
uint32_t value;
};
typedef struct Gc_Cac_Weight_Data GcCacWeight_Data;
typedef struct {
uint32_t high;
uint32_t low;
} data_64_t;
typedef struct {
data_64_t high;
data_64_t low;
} data_128_t;
#define SMU7_CONTEXT_ID_SMC 1
#define SMU7_CONTEXT_ID_VBIOS 2
#define SMU72_MAX_LEVELS_VDDC 16
#define SMU72_MAX_LEVELS_VDDGFX 16
#define SMU72_MAX_LEVELS_VDDCI 8
#define SMU72_MAX_LEVELS_MVDD 4
#define SMU_MAX_SMIO_LEVELS 4
#define SMU72_MAX_LEVELS_GRAPHICS SMU__NUM_SCLK_DPM_STATE /* SCLK + SQ DPM + ULV */
#define SMU72_MAX_LEVELS_MEMORY SMU__NUM_MCLK_DPM_LEVELS /* MCLK Levels DPM */
#define SMU72_MAX_LEVELS_GIO SMU__NUM_LCLK_DPM_LEVELS /* LCLK Levels */
#define SMU72_MAX_LEVELS_LINK SMU__NUM_PCIE_DPM_LEVELS /* PCIe speed and number of lanes. */
#define SMU72_MAX_LEVELS_UVD 8 /* VCLK/DCLK levels for UVD. */
#define SMU72_MAX_LEVELS_VCE 8 /* ECLK levels for VCE. */
#define SMU72_MAX_LEVELS_ACP 8 /* ACLK levels for ACP. */
#define SMU72_MAX_LEVELS_SAMU 8 /* SAMCLK levels for SAMU. */
#define SMU72_MAX_ENTRIES_SMIO 32 /* Number of entries in SMIO table. */
#define DPM_NO_LIMIT 0
#define DPM_NO_UP 1
#define DPM_GO_DOWN 2
#define DPM_GO_UP 3
#define SMU7_FIRST_DPM_GRAPHICS_LEVEL 0
#define SMU7_FIRST_DPM_MEMORY_LEVEL 0
#define GPIO_CLAMP_MODE_VRHOT 1
#define GPIO_CLAMP_MODE_THERM 2
#define GPIO_CLAMP_MODE_DC 4
#define SCRATCH_B_TARG_PCIE_INDEX_SHIFT 0
#define SCRATCH_B_TARG_PCIE_INDEX_MASK (0x7<<SCRATCH_B_TARG_PCIE_INDEX_SHIFT)
#define SCRATCH_B_CURR_PCIE_INDEX_SHIFT 3
#define SCRATCH_B_CURR_PCIE_INDEX_MASK (0x7<<SCRATCH_B_CURR_PCIE_INDEX_SHIFT)
#define SCRATCH_B_TARG_UVD_INDEX_SHIFT 6
#define SCRATCH_B_TARG_UVD_INDEX_MASK (0x7<<SCRATCH_B_TARG_UVD_INDEX_SHIFT)
#define SCRATCH_B_CURR_UVD_INDEX_SHIFT 9
#define SCRATCH_B_CURR_UVD_INDEX_MASK (0x7<<SCRATCH_B_CURR_UVD_INDEX_SHIFT)
#define SCRATCH_B_TARG_VCE_INDEX_SHIFT 12
#define SCRATCH_B_TARG_VCE_INDEX_MASK (0x7<<SCRATCH_B_TARG_VCE_INDEX_SHIFT)
#define SCRATCH_B_CURR_VCE_INDEX_SHIFT 15
#define SCRATCH_B_CURR_VCE_INDEX_MASK (0x7<<SCRATCH_B_CURR_VCE_INDEX_SHIFT)
#define SCRATCH_B_TARG_ACP_INDEX_SHIFT 18
#define SCRATCH_B_TARG_ACP_INDEX_MASK (0x7<<SCRATCH_B_TARG_ACP_INDEX_SHIFT)
#define SCRATCH_B_CURR_ACP_INDEX_SHIFT 21
#define SCRATCH_B_CURR_ACP_INDEX_MASK (0x7<<SCRATCH_B_CURR_ACP_INDEX_SHIFT)
#define SCRATCH_B_TARG_SAMU_INDEX_SHIFT 24
#define SCRATCH_B_TARG_SAMU_INDEX_MASK (0x7<<SCRATCH_B_TARG_SAMU_INDEX_SHIFT)
#define SCRATCH_B_CURR_SAMU_INDEX_SHIFT 27
#define SCRATCH_B_CURR_SAMU_INDEX_MASK (0x7<<SCRATCH_B_CURR_SAMU_INDEX_SHIFT)
/* Virtualization Defines */
#define CG_XDMA_MASK 0x1
#define CG_XDMA_SHIFT 0
#define CG_UVD_MASK 0x2
#define CG_UVD_SHIFT 1
#define CG_VCE_MASK 0x4
#define CG_VCE_SHIFT 2
#define CG_SAMU_MASK 0x8
#define CG_SAMU_SHIFT 3
#define CG_GFX_MASK 0x10
#define CG_GFX_SHIFT 4
#define CG_SDMA_MASK 0x20
#define CG_SDMA_SHIFT 5
#define CG_HDP_MASK 0x40
#define CG_HDP_SHIFT 6
#define CG_MC_MASK 0x80
#define CG_MC_SHIFT 7
#define CG_DRM_MASK 0x100
#define CG_DRM_SHIFT 8
#define CG_ROM_MASK 0x200
#define CG_ROM_SHIFT 9
#define CG_BIF_MASK 0x400
#define CG_BIF_SHIFT 10
#define SMU72_DTE_ITERATIONS 5
#define SMU72_DTE_SOURCES 3
#define SMU72_DTE_SINKS 1
#define SMU72_NUM_CPU_TES 0
#define SMU72_NUM_GPU_TES 1
#define SMU72_NUM_NON_TES 2
#define SMU72_DTE_FAN_SCALAR_MIN 0x100
#define SMU72_DTE_FAN_SCALAR_MAX 0x166
#define SMU72_DTE_FAN_TEMP_MAX 93
#define SMU72_DTE_FAN_TEMP_MIN 83
#if defined SMU__FUSION_ONLY
#define SMU7_DTE_ITERATIONS 5
#define SMU7_DTE_SOURCES 5
#define SMU7_DTE_SINKS 3
#define SMU7_NUM_CPU_TES 2
#define SMU7_NUM_GPU_TES 1
#define SMU7_NUM_NON_TES 2
#endif
struct SMU7_HystController_Data {
uint8_t waterfall_up;
uint8_t waterfall_down;
uint8_t waterfall_limit;
uint8_t spare;
uint16_t release_cnt;
uint16_t release_limit;
};
typedef struct SMU7_HystController_Data SMU7_HystController_Data;
struct SMU72_PIDController {
uint32_t Ki;
int32_t LFWindupUpperLim;
int32_t LFWindupLowerLim;
uint32_t StatePrecision;
uint32_t LfPrecision;
uint32_t LfOffset;
uint32_t MaxState;
uint32_t MaxLfFraction;
uint32_t StateShift;
};
typedef struct SMU72_PIDController SMU72_PIDController;
struct SMU7_LocalDpmScoreboard {
uint32_t PercentageBusy;
int32_t PIDError;
int32_t PIDIntegral;
int32_t PIDOutput;
uint32_t SigmaDeltaAccum;
uint32_t SigmaDeltaOutput;
uint32_t SigmaDeltaLevel;
uint32_t UtilizationSetpoint;
uint8_t TdpClampMode;
uint8_t TdcClampMode;
uint8_t ThermClampMode;
uint8_t VoltageBusy;
int8_t CurrLevel;
int8_t TargLevel;
uint8_t LevelChangeInProgress;
uint8_t UpHyst;
uint8_t DownHyst;
uint8_t VoltageDownHyst;
uint8_t DpmEnable;
uint8_t DpmRunning;
uint8_t DpmForce;
uint8_t DpmForceLevel;
uint8_t DisplayWatermark;
uint8_t McArbIndex;
uint32_t MinimumPerfSclk;
uint8_t AcpiReq;
uint8_t AcpiAck;
uint8_t GfxClkSlow;
uint8_t GpioClampMode; /* bit0 = VRHOT: bit1 = THERM: bit2 = DC */
uint8_t FpsFilterWeight;
uint8_t EnabledLevelsChange;
uint8_t DteClampMode;
uint8_t FpsClampMode;
uint16_t LevelResidencyCounters[SMU72_MAX_LEVELS_GRAPHICS];
uint16_t LevelSwitchCounters[SMU72_MAX_LEVELS_GRAPHICS];
void (*TargetStateCalculator)(uint8_t);
void (*SavedTargetStateCalculator)(uint8_t);
uint16_t AutoDpmInterval;
uint16_t AutoDpmRange;
uint8_t FpsEnabled;
uint8_t MaxPerfLevel;
uint8_t AllowLowClkInterruptToHost;
uint8_t FpsRunning;
uint32_t MaxAllowedFrequency;
uint32_t FilteredSclkFrequency;
uint32_t LastSclkFrequency;
uint32_t FilteredSclkFrequencyCnt;
};
typedef struct SMU7_LocalDpmScoreboard SMU7_LocalDpmScoreboard;
#define SMU7_MAX_VOLTAGE_CLIENTS 12
typedef uint8_t (*VoltageChangeHandler_t)(uint16_t, uint8_t);
struct SMU_VoltageLevel {
uint8_t Vddc;
uint8_t Vddci;
uint8_t VddGfx;
uint8_t Phases;
};
typedef struct SMU_VoltageLevel SMU_VoltageLevel;
struct SMU7_VoltageScoreboard {
SMU_VoltageLevel CurrentVoltage;
SMU_VoltageLevel TargetVoltage;
uint16_t MaxVid;
uint8_t HighestVidOffset;
uint8_t CurrentVidOffset;
uint8_t ControllerBusy;
uint8_t CurrentVid;
uint8_t CurrentVddciVid;
uint8_t VddGfxShutdown; /* 0 = normal mode, 1 = shut down */
SMU_VoltageLevel RequestedVoltage[SMU7_MAX_VOLTAGE_CLIENTS];
uint8_t EnabledRequest[SMU7_MAX_VOLTAGE_CLIENTS];
uint8_t TargetIndex;
uint8_t Delay;
uint8_t ControllerEnable;
uint8_t ControllerRunning;
uint16_t CurrentStdVoltageHiSidd;
uint16_t CurrentStdVoltageLoSidd;
uint8_t OverrideVoltage;
uint8_t VddcUseUlvOffset;
uint8_t VddGfxUseUlvOffset;
uint8_t padding;
VoltageChangeHandler_t ChangeVddc;
VoltageChangeHandler_t ChangeVddGfx;
VoltageChangeHandler_t ChangeVddci;
VoltageChangeHandler_t ChangePhase;
VoltageChangeHandler_t ChangeMvdd;
VoltageChangeHandler_t functionLinks[6];
uint8_t *VddcFollower1;
uint8_t *VddcFollower2;
int16_t Driver_OD_RequestedVidOffset1;
int16_t Driver_OD_RequestedVidOffset2;
};
typedef struct SMU7_VoltageScoreboard SMU7_VoltageScoreboard;
#define SMU7_MAX_PCIE_LINK_SPEEDS 3 /* 0:Gen1 1:Gen2 2:Gen3 */
struct SMU7_PCIeLinkSpeedScoreboard {
uint8_t DpmEnable;
uint8_t DpmRunning;
uint8_t DpmForce;
uint8_t DpmForceLevel;
uint8_t CurrentLinkSpeed;
uint8_t EnabledLevelsChange;
uint16_t AutoDpmInterval;
uint16_t AutoDpmRange;
uint16_t AutoDpmCount;
uint8_t DpmMode;
uint8_t AcpiReq;
uint8_t AcpiAck;
uint8_t CurrentLinkLevel;
};
typedef struct SMU7_PCIeLinkSpeedScoreboard SMU7_PCIeLinkSpeedScoreboard;
/* -------------------------------------------------------- CAC table ------------------------------------------------------ */
#define SMU7_LKGE_LUT_NUM_OF_TEMP_ENTRIES 16
#define SMU7_LKGE_LUT_NUM_OF_VOLT_ENTRIES 16
#define SMU7_SCALE_I 7
#define SMU7_SCALE_R 12
struct SMU7_PowerScoreboard {
PowerCalculatorData_t VddGfxPowerData[SID_OPTION_COUNT];
PowerCalculatorData_t VddcPowerData[SID_OPTION_COUNT];
uint32_t TotalGpuPower;
uint32_t TdcCurrent;
uint16_t VddciTotalPower;
uint16_t sparesasfsdfd;
uint16_t Vddr1Power;
uint16_t RocPower;
uint16_t CalcMeasPowerBlend;
uint8_t SidOptionPower;
uint8_t SidOptionCurrent;
uint32_t WinTime;
uint16_t Telemetry_1_slope;
uint16_t Telemetry_2_slope;
int32_t Telemetry_1_offset;
int32_t Telemetry_2_offset;
uint32_t VddcCurrentTelemetry;
uint32_t VddGfxCurrentTelemetry;
uint32_t VddcPowerTelemetry;
uint32_t VddGfxPowerTelemetry;
uint32_t VddciPowerTelemetry;
uint32_t VddcPower;
uint32_t VddGfxPower;
uint32_t VddciPower;
uint32_t TelemetryCurrent[2];
uint32_t TelemetryVoltage[2];
uint32_t TelemetryPower[2];
};
typedef struct SMU7_PowerScoreboard SMU7_PowerScoreboard;
struct SMU7_ThermalScoreboard {
int16_t GpuLimit;
int16_t GpuHyst;
uint16_t CurrGnbTemp;
uint16_t FilteredGnbTemp;
uint8_t ControllerEnable;
uint8_t ControllerRunning;
uint8_t AutoTmonCalInterval;
uint8_t AutoTmonCalEnable;
uint8_t ThermalDpmEnabled;
uint8_t SclkEnabledMask;
uint8_t spare[2];
int32_t temperature_gradient;
SMU7_HystController_Data HystControllerData;
int32_t WeightedSensorTemperature;
uint16_t TemperatureLimit[SMU72_MAX_LEVELS_GRAPHICS];
uint32_t Alpha;
};
typedef struct SMU7_ThermalScoreboard SMU7_ThermalScoreboard;
/* For FeatureEnables: */
#define SMU7_SCLK_DPM_CONFIG_MASK 0x01
#define SMU7_VOLTAGE_CONTROLLER_CONFIG_MASK 0x02
#define SMU7_THERMAL_CONTROLLER_CONFIG_MASK 0x04
#define SMU7_MCLK_DPM_CONFIG_MASK 0x08
#define SMU7_UVD_DPM_CONFIG_MASK 0x10
#define SMU7_VCE_DPM_CONFIG_MASK 0x20
#define SMU7_ACP_DPM_CONFIG_MASK 0x40
#define SMU7_SAMU_DPM_CONFIG_MASK 0x80
#define SMU7_PCIEGEN_DPM_CONFIG_MASK 0x100
#define SMU7_ACP_MCLK_HANDSHAKE_DISABLE 0x00000001
#define SMU7_ACP_SCLK_HANDSHAKE_DISABLE 0x00000002
#define SMU7_UVD_MCLK_HANDSHAKE_DISABLE 0x00000100
#define SMU7_UVD_SCLK_HANDSHAKE_DISABLE 0x00000200
#define SMU7_VCE_MCLK_HANDSHAKE_DISABLE 0x00010000
#define SMU7_VCE_SCLK_HANDSHAKE_DISABLE 0x00020000
/* All 'soft registers' should be uint32_t. */
struct SMU72_SoftRegisters {
uint32_t RefClockFrequency;
uint32_t PmTimerPeriod;
uint32_t FeatureEnables;
uint32_t PreVBlankGap;
uint32_t VBlankTimeout;
uint32_t TrainTimeGap;
uint32_t MvddSwitchTime;
uint32_t LongestAcpiTrainTime;
uint32_t AcpiDelay;
uint32_t G5TrainTime;
uint32_t DelayMpllPwron;
uint32_t VoltageChangeTimeout;
uint32_t HandshakeDisables;
uint8_t DisplayPhy1Config;
uint8_t DisplayPhy2Config;
uint8_t DisplayPhy3Config;
uint8_t DisplayPhy4Config;
uint8_t DisplayPhy5Config;
uint8_t DisplayPhy6Config;
uint8_t DisplayPhy7Config;
uint8_t DisplayPhy8Config;
uint32_t AverageGraphicsActivity;
uint32_t AverageMemoryActivity;
uint32_t AverageGioActivity;
uint8_t SClkDpmEnabledLevels;
uint8_t MClkDpmEnabledLevels;
uint8_t LClkDpmEnabledLevels;
uint8_t PCIeDpmEnabledLevels;
uint8_t UVDDpmEnabledLevels;
uint8_t SAMUDpmEnabledLevels;
uint8_t ACPDpmEnabledLevels;
uint8_t VCEDpmEnabledLevels;
uint32_t DRAM_LOG_ADDR_H;
uint32_t DRAM_LOG_ADDR_L;
uint32_t DRAM_LOG_PHY_ADDR_H;
uint32_t DRAM_LOG_PHY_ADDR_L;
uint32_t DRAM_LOG_BUFF_SIZE;
uint32_t UlvEnterCount;
uint32_t UlvTime;
uint32_t UcodeLoadStatus;
uint32_t Reserved[2];
};
typedef struct SMU72_SoftRegisters SMU72_SoftRegisters;
struct SMU72_Firmware_Header {
uint32_t Digest[5];
uint32_t Version;
uint32_t HeaderSize;
uint32_t Flags;
uint32_t EntryPoint;
uint32_t CodeSize;
uint32_t ImageSize;
uint32_t Rtos;
uint32_t SoftRegisters;
uint32_t DpmTable;
uint32_t FanTable;
uint32_t CacConfigTable;
uint32_t CacStatusTable;
uint32_t mcRegisterTable;
uint32_t mcArbDramTimingTable;
uint32_t PmFuseTable;
uint32_t Globals;
uint32_t ClockStretcherTable;
uint32_t Reserved[41];
uint32_t Signature;
};
typedef struct SMU72_Firmware_Header SMU72_Firmware_Header;
#define SMU72_FIRMWARE_HEADER_LOCATION 0x20000
enum DisplayConfig {
PowerDown = 1,
DP54x4,
DP54x2,
DP54x1,
DP27x4,
DP27x2,
DP27x1,
HDMI297,
HDMI162,
LVDS,
DP324x4,
DP324x2,
DP324x1
};
#define MC_BLOCK_COUNT 1
#define CPL_BLOCK_COUNT 5
#define SE_BLOCK_COUNT 15
#define GC_BLOCK_COUNT 24
struct SMU7_Local_Cac {
uint8_t BlockId;
uint8_t SignalId;
uint8_t Threshold;
uint8_t Padding;
};
typedef struct SMU7_Local_Cac SMU7_Local_Cac;
struct SMU7_Local_Cac_Table {
SMU7_Local_Cac CplLocalCac[CPL_BLOCK_COUNT];
SMU7_Local_Cac McLocalCac[MC_BLOCK_COUNT];
SMU7_Local_Cac SeLocalCac[SE_BLOCK_COUNT];
SMU7_Local_Cac GcLocalCac[GC_BLOCK_COUNT];
};
typedef struct SMU7_Local_Cac_Table SMU7_Local_Cac_Table;
#if !defined(SMC_MICROCODE)
#pragma pack(pop)
#endif
/* Description of Clock Gating bitmask for Tonga: */
/* System Clock Gating */
#define CG_SYS_BITMASK_FIRST_BIT 0 /* First bit of Sys CG bitmask */
#define CG_SYS_BITMASK_LAST_BIT 9 /* Last bit of Sys CG bitmask */
#define CG_SYS_BIF_MGLS_SHIFT 0
#define CG_SYS_ROM_SHIFT 1
#define CG_SYS_MC_MGCG_SHIFT 2
#define CG_SYS_MC_MGLS_SHIFT 3
#define CG_SYS_SDMA_MGCG_SHIFT 4
#define CG_SYS_SDMA_MGLS_SHIFT 5
#define CG_SYS_DRM_MGCG_SHIFT 6
#define CG_SYS_HDP_MGCG_SHIFT 7
#define CG_SYS_HDP_MGLS_SHIFT 8
#define CG_SYS_DRM_MGLS_SHIFT 9
#define CG_SYS_BIF_MGLS_MASK 0x1
#define CG_SYS_ROM_MASK 0x2
#define CG_SYS_MC_MGCG_MASK 0x4
#define CG_SYS_MC_MGLS_MASK 0x8
#define CG_SYS_SDMA_MGCG_MASK 0x10
#define CG_SYS_SDMA_MGLS_MASK 0x20
#define CG_SYS_DRM_MGCG_MASK 0x40
#define CG_SYS_HDP_MGCG_MASK 0x80
#define CG_SYS_HDP_MGLS_MASK 0x100
#define CG_SYS_DRM_MGLS_MASK 0x200
/* Graphics Clock Gating */
#define CG_GFX_BITMASK_FIRST_BIT 16 /* First bit of Gfx CG bitmask */
#define CG_GFX_BITMASK_LAST_BIT 20 /* Last bit of Gfx CG bitmask */
#define CG_GFX_CGCG_SHIFT 16
#define CG_GFX_CGLS_SHIFT 17
#define CG_CPF_MGCG_SHIFT 18
#define CG_RLC_MGCG_SHIFT 19
#define CG_GFX_OTHERS_MGCG_SHIFT 20
#define CG_GFX_CGCG_MASK 0x00010000
#define CG_GFX_CGLS_MASK 0x00020000
#define CG_CPF_MGCG_MASK 0x00040000
#define CG_RLC_MGCG_MASK 0x00080000
#define CG_GFX_OTHERS_MGCG_MASK 0x00100000
/* Voltage Regulator Configuration */
/* VR Config info is contained in dpmTable.VRConfig */
#define VRCONF_VDDC_MASK 0x000000FF
#define VRCONF_VDDC_SHIFT 0
#define VRCONF_VDDGFX_MASK 0x0000FF00
#define VRCONF_VDDGFX_SHIFT 8
#define VRCONF_VDDCI_MASK 0x00FF0000
#define VRCONF_VDDCI_SHIFT 16
#define VRCONF_MVDD_MASK 0xFF000000
#define VRCONF_MVDD_SHIFT 24
#define VR_MERGED_WITH_VDDC 0
#define VR_SVI2_PLANE_1 1
#define VR_SVI2_PLANE_2 2
#define VR_SMIO_PATTERN_1 3
#define VR_SMIO_PATTERN_2 4
#define VR_STATIC_VOLTAGE 5
/* Clock Stretcher Configuration */
#define CLOCK_STRETCHER_MAX_ENTRIES 0x4
#define CKS_LOOKUPTable_MAX_ENTRIES 0x4
/* The 'settings' field is subdivided in the following way: */
#define CLOCK_STRETCHER_SETTING_DDT_MASK 0x01
#define CLOCK_STRETCHER_SETTING_DDT_SHIFT 0x0
#define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_MASK 0x1E
#define CLOCK_STRETCHER_SETTING_STRETCH_AMOUNT_SHIFT 0x1
#define CLOCK_STRETCHER_SETTING_ENABLE_MASK 0x80
#define CLOCK_STRETCHER_SETTING_ENABLE_SHIFT 0x7
struct SMU_ClockStretcherDataTableEntry {
uint8_t minVID;
uint8_t maxVID;
uint16_t setting;
};
typedef struct SMU_ClockStretcherDataTableEntry SMU_ClockStretcherDataTableEntry;
struct SMU_ClockStretcherDataTable {
SMU_ClockStretcherDataTableEntry ClockStretcherDataTableEntry[CLOCK_STRETCHER_MAX_ENTRIES];
};
typedef struct SMU_ClockStretcherDataTable SMU_ClockStretcherDataTable;
struct SMU_CKS_LOOKUPTableEntry {
uint16_t minFreq;
uint16_t maxFreq;
uint8_t setting;
uint8_t padding[3];
};
typedef struct SMU_CKS_LOOKUPTableEntry SMU_CKS_LOOKUPTableEntry;
struct SMU_CKS_LOOKUPTable {
SMU_CKS_LOOKUPTableEntry CKS_LOOKUPTableEntry[CKS_LOOKUPTable_MAX_ENTRIES];
};
typedef struct SMU_CKS_LOOKUPTable SMU_CKS_LOOKUPTable;
#endif

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#ifndef SMU72_DISCRETE_H
#define SMU72_DISCRETE_H
#include "smu72.h"
#if !defined(SMC_MICROCODE)
#pragma pack(push, 1)
#endif
struct SMIO_Pattern {
uint16_t Voltage;
uint8_t Smio;
uint8_t padding;
};
typedef struct SMIO_Pattern SMIO_Pattern;
struct SMIO_Table {
SMIO_Pattern Pattern[SMU_MAX_SMIO_LEVELS];
};
typedef struct SMIO_Table SMIO_Table;
struct SMU72_Discrete_GraphicsLevel {
SMU_VoltageLevel MinVoltage;
uint32_t SclkFrequency;
uint8_t pcieDpmLevel;
uint8_t DeepSleepDivId;
uint16_t ActivityLevel;
uint32_t CgSpllFuncCntl3;
uint32_t CgSpllFuncCntl4;
uint32_t SpllSpreadSpectrum;
uint32_t SpllSpreadSpectrum2;
uint32_t CcPwrDynRm;
uint32_t CcPwrDynRm1;
uint8_t SclkDid;
uint8_t DisplayWatermark;
uint8_t EnabledForActivity;
uint8_t EnabledForThrottle;
uint8_t UpHyst;
uint8_t DownHyst;
uint8_t VoltageDownHyst;
uint8_t PowerThrottle;
};
typedef struct SMU72_Discrete_GraphicsLevel SMU72_Discrete_GraphicsLevel;
struct SMU72_Discrete_ACPILevel {
uint32_t Flags;
SMU_VoltageLevel MinVoltage;
uint32_t SclkFrequency;
uint8_t SclkDid;
uint8_t DisplayWatermark;
uint8_t DeepSleepDivId;
uint8_t padding;
uint32_t CgSpllFuncCntl;
uint32_t CgSpllFuncCntl2;
uint32_t CgSpllFuncCntl3;
uint32_t CgSpllFuncCntl4;
uint32_t SpllSpreadSpectrum;
uint32_t SpllSpreadSpectrum2;
uint32_t CcPwrDynRm;
uint32_t CcPwrDynRm1;
};
typedef struct SMU72_Discrete_ACPILevel SMU72_Discrete_ACPILevel;
struct SMU72_Discrete_Ulv {
uint32_t CcPwrDynRm;
uint32_t CcPwrDynRm1;
uint16_t VddcOffset;
uint8_t VddcOffsetVid;
uint8_t VddcPhase;
uint32_t Reserved;
};
typedef struct SMU72_Discrete_Ulv SMU72_Discrete_Ulv;
struct SMU72_Discrete_MemoryLevel {
SMU_VoltageLevel MinVoltage;
uint32_t MinMvdd;
uint32_t MclkFrequency;
uint8_t EdcReadEnable;
uint8_t EdcWriteEnable;
uint8_t RttEnable;
uint8_t StutterEnable;
uint8_t StrobeEnable;
uint8_t StrobeRatio;
uint8_t EnabledForThrottle;
uint8_t EnabledForActivity;
uint8_t UpHyst;
uint8_t DownHyst;
uint8_t VoltageDownHyst;
uint8_t padding;
uint16_t ActivityLevel;
uint8_t DisplayWatermark;
uint8_t padding1;
uint32_t MpllFuncCntl;
uint32_t MpllFuncCntl_1;
uint32_t MpllFuncCntl_2;
uint32_t MpllAdFuncCntl;
uint32_t MpllDqFuncCntl;
uint32_t MclkPwrmgtCntl;
uint32_t DllCntl;
uint32_t MpllSs1;
uint32_t MpllSs2;
};
typedef struct SMU72_Discrete_MemoryLevel SMU72_Discrete_MemoryLevel;
struct SMU72_Discrete_LinkLevel {
uint8_t PcieGenSpeed; /*< 0:PciE-gen1 1:PciE-gen2 2:PciE-gen3 */
uint8_t PcieLaneCount; /*< 1=x1, 2=x2, 3=x4, 4=x8, 5=x12, 6=x16 */
uint8_t EnabledForActivity;
uint8_t SPC;
uint32_t DownThreshold;
uint32_t UpThreshold;
uint32_t Reserved;
};
typedef struct SMU72_Discrete_LinkLevel SMU72_Discrete_LinkLevel;
/* MC ARB DRAM Timing registers. */
struct SMU72_Discrete_MCArbDramTimingTableEntry {
uint32_t McArbDramTiming;
uint32_t McArbDramTiming2;
uint8_t McArbBurstTime;
uint8_t padding[3];
};
typedef struct SMU72_Discrete_MCArbDramTimingTableEntry SMU72_Discrete_MCArbDramTimingTableEntry;
struct SMU72_Discrete_MCArbDramTimingTable {
SMU72_Discrete_MCArbDramTimingTableEntry entries[SMU__NUM_SCLK_DPM_STATE][SMU__NUM_MCLK_DPM_LEVELS];
};
typedef struct SMU72_Discrete_MCArbDramTimingTable SMU72_Discrete_MCArbDramTimingTable;
/* UVD VCLK/DCLK state (level) definition. */
struct SMU72_Discrete_UvdLevel {
uint32_t VclkFrequency;
uint32_t DclkFrequency;
SMU_VoltageLevel MinVoltage;
uint8_t VclkDivider;
uint8_t DclkDivider;
uint8_t padding[2];
};
typedef struct SMU72_Discrete_UvdLevel SMU72_Discrete_UvdLevel;
/* Clocks for other external blocks (VCE, ACP, SAMU). */
struct SMU72_Discrete_ExtClkLevel {
uint32_t Frequency;
SMU_VoltageLevel MinVoltage;
uint8_t Divider;
uint8_t padding[3];
};
typedef struct SMU72_Discrete_ExtClkLevel SMU72_Discrete_ExtClkLevel;
struct SMU72_Discrete_StateInfo {
uint32_t SclkFrequency;
uint32_t MclkFrequency;
uint32_t VclkFrequency;
uint32_t DclkFrequency;
uint32_t SamclkFrequency;
uint32_t AclkFrequency;
uint32_t EclkFrequency;
uint16_t MvddVoltage;
uint16_t padding16;
uint8_t DisplayWatermark;
uint8_t McArbIndex;
uint8_t McRegIndex;
uint8_t SeqIndex;
uint8_t SclkDid;
int8_t SclkIndex;
int8_t MclkIndex;
uint8_t PCIeGen;
};
typedef struct SMU72_Discrete_StateInfo SMU72_Discrete_StateInfo;
struct SMU72_Discrete_DpmTable {
/* Multi-DPM controller settings */
SMU72_PIDController GraphicsPIDController;
SMU72_PIDController MemoryPIDController;
SMU72_PIDController LinkPIDController;
uint32_t SystemFlags;
/* SMIO masks for voltage and phase controls */
uint32_t VRConfig;
uint32_t SmioMask1;
uint32_t SmioMask2;
SMIO_Table SmioTable1;
SMIO_Table SmioTable2;
uint32_t VddcLevelCount;
uint32_t VddciLevelCount;
uint32_t VddGfxLevelCount;
uint32_t MvddLevelCount;
uint16_t VddcTable[SMU72_MAX_LEVELS_VDDC];
uint16_t VddGfxTable[SMU72_MAX_LEVELS_VDDGFX];
uint16_t VddciTable[SMU72_MAX_LEVELS_VDDCI];
uint8_t BapmVddGfxVidHiSidd[SMU72_MAX_LEVELS_VDDGFX];
uint8_t BapmVddGfxVidLoSidd[SMU72_MAX_LEVELS_VDDGFX];
uint8_t BapmVddGfxVidHiSidd2[SMU72_MAX_LEVELS_VDDGFX];
uint8_t BapmVddcVidHiSidd[SMU72_MAX_LEVELS_VDDC];
uint8_t BapmVddcVidLoSidd[SMU72_MAX_LEVELS_VDDC];
uint8_t BapmVddcVidHiSidd2[SMU72_MAX_LEVELS_VDDC];
uint8_t GraphicsDpmLevelCount;
uint8_t MemoryDpmLevelCount;
uint8_t LinkLevelCount;
uint8_t MasterDeepSleepControl;
uint8_t UvdLevelCount;
uint8_t VceLevelCount;
uint8_t AcpLevelCount;
uint8_t SamuLevelCount;
uint8_t ThermOutGpio;
uint8_t ThermOutPolarity;
uint8_t ThermOutMode;
uint8_t DPMFreezeAndForced;
uint32_t Reserved[4];
/* State table entries for each DPM state */
SMU72_Discrete_GraphicsLevel GraphicsLevel[SMU72_MAX_LEVELS_GRAPHICS];
SMU72_Discrete_MemoryLevel MemoryACPILevel;
SMU72_Discrete_MemoryLevel MemoryLevel[SMU72_MAX_LEVELS_MEMORY];
SMU72_Discrete_LinkLevel LinkLevel[SMU72_MAX_LEVELS_LINK];
SMU72_Discrete_ACPILevel ACPILevel;
SMU72_Discrete_UvdLevel UvdLevel[SMU72_MAX_LEVELS_UVD];
SMU72_Discrete_ExtClkLevel VceLevel[SMU72_MAX_LEVELS_VCE];
SMU72_Discrete_ExtClkLevel AcpLevel[SMU72_MAX_LEVELS_ACP];
SMU72_Discrete_ExtClkLevel SamuLevel[SMU72_MAX_LEVELS_SAMU];
SMU72_Discrete_Ulv Ulv;
uint32_t SclkStepSize;
uint32_t Smio[SMU72_MAX_ENTRIES_SMIO];
uint8_t UvdBootLevel;
uint8_t VceBootLevel;
uint8_t AcpBootLevel;
uint8_t SamuBootLevel;
uint8_t GraphicsBootLevel;
uint8_t GraphicsVoltageChangeEnable;
uint8_t GraphicsThermThrottleEnable;
uint8_t GraphicsInterval;
uint8_t VoltageInterval;
uint8_t ThermalInterval;
uint16_t TemperatureLimitHigh;
uint16_t TemperatureLimitLow;
uint8_t MemoryBootLevel;
uint8_t MemoryVoltageChangeEnable;
uint16_t BootMVdd;
uint8_t MemoryInterval;
uint8_t MemoryThermThrottleEnable;
uint16_t VoltageResponseTime;
uint16_t PhaseResponseTime;
uint8_t PCIeBootLinkLevel;
uint8_t PCIeGenInterval;
uint8_t DTEInterval;
uint8_t DTEMode;
uint8_t SVI2Enable;
uint8_t VRHotGpio;
uint8_t AcDcGpio;
uint8_t ThermGpio;
uint16_t PPM_PkgPwrLimit;
uint16_t PPM_TemperatureLimit;
uint16_t DefaultTdp;
uint16_t TargetTdp;
uint16_t FpsHighThreshold;
uint16_t FpsLowThreshold;
uint16_t BAPMTI_R[SMU72_DTE_ITERATIONS][SMU72_DTE_SOURCES][SMU72_DTE_SINKS];
uint16_t BAPMTI_RC[SMU72_DTE_ITERATIONS][SMU72_DTE_SOURCES][SMU72_DTE_SINKS];
uint8_t DTEAmbientTempBase;
uint8_t DTETjOffset;
uint8_t GpuTjMax;
uint8_t GpuTjHyst;
SMU_VoltageLevel BootVoltage;
uint32_t BAPM_TEMP_GRADIENT;
uint32_t LowSclkInterruptThreshold;
uint32_t VddGfxReChkWait;
uint8_t ClockStretcherAmount;
uint8_t Sclk_CKS_masterEn0_7;
uint8_t Sclk_CKS_masterEn8_15;
uint8_t padding[1];
uint8_t Sclk_voltageOffset[8];
SMU_ClockStretcherDataTable ClockStretcherDataTable;
SMU_CKS_LOOKUPTable CKS_LOOKUPTable;
};
typedef struct SMU72_Discrete_DpmTable SMU72_Discrete_DpmTable;
/* --------------------------------------------------- AC Timing Parameters ------------------------------------------------ */
#define SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE 16
#define SMU72_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT SMU72_MAX_LEVELS_MEMORY /* DPM */
struct SMU72_Discrete_MCRegisterAddress {
uint16_t s0;
uint16_t s1;
};
typedef struct SMU72_Discrete_MCRegisterAddress SMU72_Discrete_MCRegisterAddress;
struct SMU72_Discrete_MCRegisterSet {
uint32_t value[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE];
};
typedef struct SMU72_Discrete_MCRegisterSet SMU72_Discrete_MCRegisterSet;
struct SMU72_Discrete_MCRegisters {
uint8_t last;
uint8_t reserved[3];
SMU72_Discrete_MCRegisterAddress address[SMU72_DISCRETE_MC_REGISTER_ARRAY_SIZE];
SMU72_Discrete_MCRegisterSet data[SMU72_DISCRETE_MC_REGISTER_ARRAY_SET_COUNT];
};
typedef struct SMU72_Discrete_MCRegisters SMU72_Discrete_MCRegisters;
/* --------------------------------------------------- Fan Table ----------------------------------------------------------- */
struct SMU72_Discrete_FanTable {
uint16_t FdoMode;
int16_t TempMin;
int16_t TempMed;
int16_t TempMax;
int16_t Slope1;
int16_t Slope2;
int16_t FdoMin;
int16_t HystUp;
int16_t HystDown;
int16_t HystSlope;
int16_t TempRespLim;
int16_t TempCurr;
int16_t SlopeCurr;
int16_t PwmCurr;
uint32_t RefreshPeriod;
int16_t FdoMax;
uint8_t TempSrc;
int8_t FanControl_GL_Flag;
};
typedef struct SMU72_Discrete_FanTable SMU72_Discrete_FanTable;
#define SMU7_DISCRETE_GPIO_SCLK_DEBUG 4
#define SMU7_DISCRETE_GPIO_SCLK_DEBUG_BIT (0x1 << SMU7_DISCRETE_GPIO_SCLK_DEBUG)
struct SMU7_MclkDpmScoreboard {
uint32_t PercentageBusy;
int32_t PIDError;
int32_t PIDIntegral;
int32_t PIDOutput;
uint32_t SigmaDeltaAccum;
uint32_t SigmaDeltaOutput;
uint32_t SigmaDeltaLevel;
uint32_t UtilizationSetpoint;
uint8_t TdpClampMode;
uint8_t TdcClampMode;
uint8_t ThermClampMode;
uint8_t VoltageBusy;
int8_t CurrLevel;
int8_t TargLevel;
uint8_t LevelChangeInProgress;
uint8_t UpHyst;
uint8_t DownHyst;
uint8_t VoltageDownHyst;
uint8_t DpmEnable;
uint8_t DpmRunning;
uint8_t DpmForce;
uint8_t DpmForceLevel;
uint8_t DisplayWatermark;
uint8_t McArbIndex;
uint32_t MinimumPerfMclk;
uint8_t AcpiReq;
uint8_t AcpiAck;
uint8_t MclkSwitchInProgress;
uint8_t MclkSwitchCritical;
uint8_t IgnoreVBlank;
uint8_t TargetMclkIndex;
uint8_t TargetMvddIndex;
uint8_t MclkSwitchResult;
uint16_t VbiFailureCount;
uint8_t VbiWaitCounter;
uint8_t EnabledLevelsChange;
uint16_t LevelResidencyCountersN[SMU72_MAX_LEVELS_MEMORY];
uint16_t LevelSwitchCounters[SMU72_MAX_LEVELS_MEMORY];
void (*TargetStateCalculator)(uint8_t);
void (*SavedTargetStateCalculator)(uint8_t);
uint16_t AutoDpmInterval;
uint16_t AutoDpmRange;
uint16_t VbiTimeoutCount;
uint16_t MclkSwitchingTime;
uint8_t fastSwitch;
uint8_t Save_PIC_VDDGFX_EXIT;
uint8_t Save_PIC_VDDGFX_ENTER;
uint8_t padding;
};
typedef struct SMU7_MclkDpmScoreboard SMU7_MclkDpmScoreboard;
struct SMU7_UlvScoreboard {
uint8_t EnterUlv;
uint8_t ExitUlv;
uint8_t UlvActive;
uint8_t WaitingForUlv;
uint8_t UlvEnable;
uint8_t UlvRunning;
uint8_t UlvMasterEnable;
uint8_t padding;
uint32_t UlvAbortedCount;
uint32_t UlvTimeStamp;
};
typedef struct SMU7_UlvScoreboard SMU7_UlvScoreboard;
struct VddgfxSavedRegisters {
uint32_t GPU_DBG[3];
uint32_t MEC_BaseAddress_Hi;
uint32_t MEC_BaseAddress_Lo;
uint32_t THM_TMON0_CTRL2__RDIR_PRESENT;
uint32_t THM_TMON1_CTRL2__RDIR_PRESENT;
uint32_t CP_INT_CNTL;
};
typedef struct VddgfxSavedRegisters VddgfxSavedRegisters;
struct SMU7_VddGfxScoreboard {
uint8_t VddGfxEnable;
uint8_t VddGfxActive;
uint8_t VPUResetOccured;
uint8_t padding;
uint32_t VddGfxEnteredCount;
uint32_t VddGfxAbortedCount;
uint32_t VddGfxVid;
VddgfxSavedRegisters SavedRegisters;
};
typedef struct SMU7_VddGfxScoreboard SMU7_VddGfxScoreboard;
struct SMU7_TdcLimitScoreboard {
uint8_t Enable;
uint8_t Running;
uint16_t Alpha;
uint32_t FilteredIddc;
uint32_t IddcLimit;
uint32_t IddcHyst;
SMU7_HystController_Data HystControllerData;
};
typedef struct SMU7_TdcLimitScoreboard SMU7_TdcLimitScoreboard;
struct SMU7_PkgPwrLimitScoreboard {
uint8_t Enable;
uint8_t Running;
uint16_t Alpha;
uint32_t FilteredPkgPwr;
uint32_t Limit;
uint32_t Hyst;
uint32_t LimitFromDriver;
SMU7_HystController_Data HystControllerData;
};
typedef struct SMU7_PkgPwrLimitScoreboard SMU7_PkgPwrLimitScoreboard;
struct SMU7_BapmScoreboard {
uint32_t source_powers[SMU72_DTE_SOURCES];
uint32_t source_powers_last[SMU72_DTE_SOURCES];
int32_t entity_temperatures[SMU72_NUM_GPU_TES];
int32_t initial_entity_temperatures[SMU72_NUM_GPU_TES];
int32_t Limit;
int32_t Hyst;
int32_t therm_influence_coeff_table[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS * 2];
int32_t therm_node_table[SMU72_DTE_ITERATIONS * SMU72_DTE_SOURCES * SMU72_DTE_SINKS];
uint16_t ConfigTDPPowerScalar;
uint16_t FanSpeedPowerScalar;
uint16_t OverDrivePowerScalar;
uint16_t OverDriveLimitScalar;
uint16_t FinalPowerScalar;
uint8_t VariantID;
uint8_t spare997;
SMU7_HystController_Data HystControllerData;
int32_t temperature_gradient_slope;
int32_t temperature_gradient;
uint32_t measured_temperature;
};
typedef struct SMU7_BapmScoreboard SMU7_BapmScoreboard;
struct SMU7_AcpiScoreboard {
uint32_t SavedInterruptMask[2];
uint8_t LastACPIRequest;
uint8_t CgBifResp;
uint8_t RequestType;
uint8_t Padding;
SMU72_Discrete_ACPILevel D0Level;
};
typedef struct SMU7_AcpiScoreboard SMU7_AcpiScoreboard;
struct SMU72_Discrete_PmFuses {
/* dw1 */
uint8_t SviLoadLineEn;
uint8_t SviLoadLineVddC;
uint8_t SviLoadLineTrimVddC;
uint8_t SviLoadLineOffsetVddC;
/* dw2 */
uint16_t TDC_VDDC_PkgLimit;
uint8_t TDC_VDDC_ThrottleReleaseLimitPerc;
uint8_t TDC_MAWt;
/* dw3 */
uint8_t TdcWaterfallCtl;
uint8_t LPMLTemperatureMin;
uint8_t LPMLTemperatureMax;
uint8_t Reserved;
/* dw4-dw7 */
uint8_t LPMLTemperatureScaler[16];
/* dw8-dw9 */
int16_t FuzzyFan_ErrorSetDelta;
int16_t FuzzyFan_ErrorRateSetDelta;
int16_t FuzzyFan_PwmSetDelta;
uint16_t Reserved6;
/* dw10-dw14 */
uint8_t GnbLPML[16];
/* dw15 */
uint8_t GnbLPMLMaxVid;
uint8_t GnbLPMLMinVid;
uint8_t Reserved1[2];
/* dw16 */
uint16_t BapmVddCBaseLeakageHiSidd;
uint16_t BapmVddCBaseLeakageLoSidd;
};
typedef struct SMU72_Discrete_PmFuses SMU72_Discrete_PmFuses;
struct SMU7_Discrete_Log_Header_Table {
uint32_t version;
uint32_t asic_id;
uint16_t flags;
uint16_t entry_size;
uint32_t total_size;
uint32_t num_of_entries;
uint8_t type;
uint8_t mode;
uint8_t filler_0[2];
uint32_t filler_1[2];
};
typedef struct SMU7_Discrete_Log_Header_Table SMU7_Discrete_Log_Header_Table;
struct SMU7_Discrete_Log_Cntl {
uint8_t Enabled;
uint8_t Type;
uint8_t padding[2];
uint32_t BufferSize;
uint32_t SamplesLogged;
uint32_t SampleSize;
uint32_t AddrL;
uint32_t AddrH;
};
typedef struct SMU7_Discrete_Log_Cntl SMU7_Discrete_Log_Cntl;
#define CAC_ACC_NW_NUM_OF_SIGNALS 87
struct SMU7_Discrete_Cac_Collection_Table {
uint32_t temperature;
uint32_t cac_acc_nw[CAC_ACC_NW_NUM_OF_SIGNALS];
};
typedef struct SMU7_Discrete_Cac_Collection_Table SMU7_Discrete_Cac_Collection_Table;
struct SMU7_Discrete_Cac_Verification_Table {
uint32_t VddcTotalPower;
uint32_t VddcLeakagePower;
uint32_t VddcConstantPower;
uint32_t VddcGfxDynamicPower;
uint32_t VddcUvdDynamicPower;
uint32_t VddcVceDynamicPower;
uint32_t VddcAcpDynamicPower;
uint32_t VddcPcieDynamicPower;
uint32_t VddcDceDynamicPower;
uint32_t VddcCurrent;
uint32_t VddcVoltage;
uint32_t VddciTotalPower;
uint32_t VddciLeakagePower;
uint32_t VddciConstantPower;
uint32_t VddciDynamicPower;
uint32_t Vddr1TotalPower;
uint32_t Vddr1LeakagePower;
uint32_t Vddr1ConstantPower;
uint32_t Vddr1DynamicPower;
uint32_t spare[4];
uint32_t temperature;
};
typedef struct SMU7_Discrete_Cac_Verification_Table SMU7_Discrete_Cac_Verification_Table;
struct SMU7_Discrete_Pm_Status_Table {
/* Thermal entities */
int32_t T_meas_max;
int32_t T_meas_acc;
int32_t T_calc_max;
int32_t T_calc_acc;
uint32_t P_scalar_acc;
uint32_t P_calc_max;
uint32_t P_calc_acc;
/*Voltage domains */
uint32_t I_calc_max;
uint32_t I_calc_acc;
uint32_t I_calc_acc_vddci;
uint32_t V_calc_noload_acc;
uint32_t V_calc_load_acc;
uint32_t V_calc_noload_acc_vddci;
uint32_t P_meas_acc;
uint32_t V_meas_noload_acc;
uint32_t V_meas_load_acc;
uint32_t I_meas_acc;
uint32_t P_meas_acc_vddci;
uint32_t V_meas_noload_acc_vddci;
uint32_t V_meas_load_acc_vddci;
uint32_t I_meas_acc_vddci;
/*Frequency */
uint16_t Sclk_dpm_residency[8];
uint16_t Uvd_dpm_residency[8];
uint16_t Vce_dpm_residency[8];
uint16_t Mclk_dpm_residency[4];
/*Chip */
uint32_t P_vddci_acc;
uint32_t P_vddr1_acc;
uint32_t P_nte1_acc;
uint32_t PkgPwr_max;
uint32_t PkgPwr_acc;
uint32_t MclkSwitchingTime_max;
uint32_t MclkSwitchingTime_acc;
uint32_t FanPwm_acc;
uint32_t FanRpm_acc;
uint32_t AccCnt;
};
typedef struct SMU7_Discrete_Pm_Status_Table SMU7_Discrete_Pm_Status_Table;
/*FIXME THESE NEED TO BE UPDATED */
#define SMU7_SCLK_CAC 0x561
#define SMU7_MCLK_CAC 0xF9
#define SMU7_VCLK_CAC 0x2DE
#define SMU7_DCLK_CAC 0x2DE
#define SMU7_ECLK_CAC 0x25E
#define SMU7_ACLK_CAC 0x25E
#define SMU7_SAMCLK_CAC 0x25E
#define SMU7_DISPCLK_CAC 0x100
#define SMU7_CAC_CONSTANT 0x2EE3430
#define SMU7_CAC_CONSTANT_SHIFT 18
#define SMU7_VDDCI_MCLK_CONST 1765
#define SMU7_VDDCI_MCLK_CONST_SHIFT 16
#define SMU7_VDDCI_VDDCI_CONST 50958
#define SMU7_VDDCI_VDDCI_CONST_SHIFT 14
#define SMU7_VDDCI_CONST 11781
#define SMU7_12C_VDDCI_MCLK_CONST 1623
#define SMU7_12C_VDDCI_MCLK_CONST_SHIFT 15
#define SMU7_12C_VDDCI_VDDCI_CONST 40088
#define SMU7_12C_VDDCI_VDDCI_CONST_SHIFT 13
#define SMU7_12C_VDDCI_CONST 20856
#define SMU7_VDDCI_STROBE_PWR 1331
#define SMU7_VDDR1_CONST 693
#define SMU7_VDDR1_CAC_WEIGHT 20
#define SMU7_VDDR1_CAC_WEIGHT_SHIFT 19
#define SMU7_VDDR1_STROBE_PWR 512
#define SMU7_AREA_COEFF_UVD 0xA78
#define SMU7_AREA_COEFF_VCE 0x190A
#define SMU7_AREA_COEFF_ACP 0x22D1
#define SMU7_AREA_COEFF_SAMU 0x534
/*ThermOutMode values */
#define SMU7_THERM_OUT_MODE_DISABLE 0x0
#define SMU7_THERM_OUT_MODE_THERM_ONLY 0x1
#define SMU7_THERM_OUT_MODE_THERM_VRHOT 0x2
#if !defined(SMC_MICROCODE)
#pragma pack(pop)
#endif
#endif

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drivers/gpu/drm/amd/powerplay/inc/tonga_ppsmc.h Normal file
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/*
* Copyright 2015 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef TONGA_PP_SMC_H
#define TONGA_PP_SMC_H
#pragma pack(push, 1)
#define PPSMC_SWSTATE_FLAG_DC 0x01
#define PPSMC_SWSTATE_FLAG_UVD 0x02
#define PPSMC_SWSTATE_FLAG_VCE 0x04
#define PPSMC_SWSTATE_FLAG_PCIE_X1 0x08
#define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00
#define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01
#define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff
#define PPSMC_SYSTEMFLAG_GPIO_DC 0x01
#define PPSMC_SYSTEMFLAG_STEPVDDC 0x02
#define PPSMC_SYSTEMFLAG_GDDR5 0x04
#define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP 0x08
#define PPSMC_SYSTEMFLAG_REGULATOR_HOT 0x10
#define PPSMC_SYSTEMFLAG_REGULATOR_HOT_ANALOG 0x20
#define PPSMC_SYSTEMFLAG_12CHANNEL 0x40
#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK 0x07
#define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK 0x08
#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE 0x00
#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE 0x01
#define PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH 0x10
#define PPSMC_EXTRAFLAGS_DRIVER_TO_GPIO17 0x20
#define PPSMC_EXTRAFLAGS_PCC_TO_GPIO17 0x40
/* Defines for DPM 2.0 */
#define PPSMC_DPM2FLAGS_TDPCLMP 0x01
#define PPSMC_DPM2FLAGS_PWRSHFT 0x02
#define PPSMC_DPM2FLAGS_OCP 0x04
/* Defines for display watermark level */
#define PPSMC_DISPLAY_WATERMARK_LOW 0
#define PPSMC_DISPLAY_WATERMARK_HIGH 1
/* In the HW performance level's state flags:*/
#define PPSMC_STATEFLAG_AUTO_PULSE_SKIP 0x01
#define PPSMC_STATEFLAG_POWERBOOST 0x02
#define PPSMC_STATEFLAG_PSKIP_ON_TDP_FAULT 0x04
#define PPSMC_STATEFLAG_POWERSHIFT 0x08
#define PPSMC_STATEFLAG_SLOW_READ_MARGIN 0x10
#define PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE 0x20
#define PPSMC_STATEFLAG_DEEPSLEEP_BYPASS 0x40
/* Fan control algorithm:*/
#define FDO_MODE_HARDWARE 0
#define FDO_MODE_PIECE_WISE_LINEAR 1
enum FAN_CONTROL {
FAN_CONTROL_FUZZY,
FAN_CONTROL_TABLE
};
/* Return codes for driver to SMC communication.*/
#define PPSMC_Result_OK ((uint16_t)0x01)
#define PPSMC_Result_NoMore ((uint16_t)0x02)
#define PPSMC_Result_NotNow ((uint16_t)0x03)
#define PPSMC_Result_Failed ((uint16_t)0xFF)
#define PPSMC_Result_UnknownCmd ((uint16_t)0xFE)
#define PPSMC_Result_UnknownVT ((uint16_t)0xFD)
typedef uint16_t PPSMC_Result;
#define PPSMC_isERROR(x) ((uint16_t)0x80 & (x))
#define PPSMC_MSG_Halt ((uint16_t)0x10)
#define PPSMC_MSG_Resume ((uint16_t)0x11)
#define PPSMC_MSG_EnableDPMLevel ((uint16_t)0x12)
#define PPSMC_MSG_ZeroLevelsDisabled ((uint16_t)0x13)
#define PPSMC_MSG_OneLevelsDisabled ((uint16_t)0x14)
#define PPSMC_MSG_TwoLevelsDisabled ((uint16_t)0x15)
#define PPSMC_MSG_EnableThermalInterrupt ((uint16_t)0x16)
#define PPSMC_MSG_RunningOnAC ((uint16_t)0x17)
#define PPSMC_MSG_LevelUp ((uint16_t)0x18)
#define PPSMC_MSG_LevelDown ((uint16_t)0x19)
#define PPSMC_MSG_ResetDPMCounters ((uint16_t)0x1a)
#define PPSMC_MSG_SwitchToSwState ((uint16_t)0x20)
#define PPSMC_MSG_SwitchToSwStateLast ((uint16_t)0x3f)
#define PPSMC_MSG_SwitchToInitialState ((uint16_t)0x40)
#define PPSMC_MSG_NoForcedLevel ((uint16_t)0x41)
#define PPSMC_MSG_ForceHigh ((uint16_t)0x42)
#define PPSMC_MSG_ForceMediumOrHigh ((uint16_t)0x43)
#define PPSMC_MSG_SwitchToMinimumPower ((uint16_t)0x51)
#define PPSMC_MSG_ResumeFromMinimumPower ((uint16_t)0x52)
#define PPSMC_MSG_EnableCac ((uint16_t)0x53)
#define PPSMC_MSG_DisableCac ((uint16_t)0x54)
#define PPSMC_DPMStateHistoryStart ((uint16_t)0x55)
#define PPSMC_DPMStateHistoryStop ((uint16_t)0x56)
#define PPSMC_CACHistoryStart ((uint16_t)0x57)
#define PPSMC_CACHistoryStop ((uint16_t)0x58)
#define PPSMC_TDPClampingActive ((uint16_t)0x59)
#define PPSMC_TDPClampingInactive ((uint16_t)0x5A)
#define PPSMC_StartFanControl ((uint16_t)0x5B)
#define PPSMC_StopFanControl ((uint16_t)0x5C)
#define PPSMC_NoDisplay ((uint16_t)0x5D)
#define PPSMC_HasDisplay ((uint16_t)0x5E)
#define PPSMC_MSG_UVDPowerOFF ((uint16_t)0x60)
#define PPSMC_MSG_UVDPowerON ((uint16_t)0x61)
#define PPSMC_MSG_EnableULV ((uint16_t)0x62)
#define PPSMC_MSG_DisableULV ((uint16_t)0x63)
#define PPSMC_MSG_EnterULV ((uint16_t)0x64)
#define PPSMC_MSG_ExitULV ((uint16_t)0x65)
#define PPSMC_PowerShiftActive ((uint16_t)0x6A)
#define PPSMC_PowerShiftInactive ((uint16_t)0x6B)
#define PPSMC_OCPActive ((uint16_t)0x6C)
#define PPSMC_OCPInactive ((uint16_t)0x6D)
#define PPSMC_CACLongTermAvgEnable ((uint16_t)0x6E)
#define PPSMC_CACLongTermAvgDisable ((uint16_t)0x6F)
#define PPSMC_MSG_InferredStateSweep_Start ((uint16_t)0x70)
#define PPSMC_MSG_InferredStateSweep_Stop ((uint16_t)0x71)
#define PPSMC_MSG_SwitchToLowestInfState ((uint16_t)0x72)
#define PPSMC_MSG_SwitchToNonInfState ((uint16_t)0x73)
#define PPSMC_MSG_AllStateSweep_Start ((uint16_t)0x74)
#define PPSMC_MSG_AllStateSweep_Stop ((uint16_t)0x75)
#define PPSMC_MSG_SwitchNextLowerInfState ((uint16_t)0x76)
#define PPSMC_MSG_SwitchNextHigherInfState ((uint16_t)0x77)
#define PPSMC_MSG_MclkRetrainingTest ((uint16_t)0x78)
#define PPSMC_MSG_ForceTDPClamping ((uint16_t)0x79)
#define PPSMC_MSG_CollectCAC_PowerCorreln ((uint16_t)0x7A)
#define PPSMC_MSG_CollectCAC_WeightCalib ((uint16_t)0x7B)
#define PPSMC_MSG_CollectCAC_SQonly ((uint16_t)0x7C)
#define PPSMC_MSG_CollectCAC_TemperaturePwr ((uint16_t)0x7D)
#define PPSMC_MSG_ExtremitiesTest_Start ((uint16_t)0x7E)
#define PPSMC_MSG_ExtremitiesTest_Stop ((uint16_t)0x7F)
#define PPSMC_FlushDataCache ((uint16_t)0x80)
#define PPSMC_FlushInstrCache ((uint16_t)0x81)
#define PPSMC_MSG_SetEnabledLevels ((uint16_t)0x82)
#define PPSMC_MSG_SetForcedLevels ((uint16_t)0x83)
#define PPSMC_MSG_ResetToDefaults ((uint16_t)0x84)
#define PPSMC_MSG_SetForcedLevelsAndJump ((uint16_t)0x85)
#define PPSMC_MSG_SetCACHistoryMode ((uint16_t)0x86)
#define PPSMC_MSG_EnableDTE ((uint16_t)0x87)
#define PPSMC_MSG_DisableDTE ((uint16_t)0x88)
#define PPSMC_MSG_SmcSpaceSetAddress ((uint16_t)0x89)
#define PPSMC_MSG_ChangeNearTDPLimit ((uint16_t)0x90)
#define PPSMC_MSG_ChangeSafePowerLimit ((uint16_t)0x91)
#define PPSMC_MSG_DPMStateSweepStart ((uint16_t)0x92)
#define PPSMC_MSG_DPMStateSweepStop ((uint16_t)0x93)
#define PPSMC_MSG_OVRDDisableSCLKDS ((uint16_t)0x94)
#define PPSMC_MSG_CancelDisableOVRDSCLKDS ((uint16_t)0x95)
#define PPSMC_MSG_ThrottleOVRDSCLKDS ((uint16_t)0x96)
#define PPSMC_MSG_CancelThrottleOVRDSCLKDS ((uint16_t)0x97)
#define PPSMC_MSG_GPIO17 ((uint16_t)0x98)
#define PPSMC_MSG_API_SetSvi2Volt_Vddc ((uint16_t)0x99)
#define PPSMC_MSG_API_SetSvi2Volt_Vddci ((uint16_t)0x9A)
#define PPSMC_MSG_API_SetSvi2Volt_Mvdd ((uint16_t)0x9B)
#define PPSMC_MSG_API_GetSvi2Volt_Vddc ((uint16_t)0x9C)
#define PPSMC_MSG_API_GetSvi2Volt_Vddci ((uint16_t)0x9D)
#define PPSMC_MSG_API_GetSvi2Volt_Mvdd ((uint16_t)0x9E)
#define PPSMC_MSG_BREAK ((uint16_t)0xF8)
/* Trinity Specific Messages*/
#define PPSMC_MSG_Test ((uint16_t) 0x100)
#define PPSMC_MSG_DPM_Voltage_Pwrmgt ((uint16_t) 0x101)
#define PPSMC_MSG_DPM_Config ((uint16_t) 0x102)
#define PPSMC_MSG_PM_Controller_Start ((uint16_t) 0x103)
#define PPSMC_MSG_DPM_ForceState ((uint16_t) 0x104)
#define PPSMC_MSG_PG_PowerDownSIMD ((uint16_t) 0x105)
#define PPSMC_MSG_PG_PowerUpSIMD ((uint16_t) 0x106)
#define PPSMC_MSG_PM_Controller_Stop ((uint16_t) 0x107)
#define PPSMC_MSG_PG_SIMD_Config ((uint16_t) 0x108)
#define PPSMC_MSG_Voltage_Cntl_Enable ((uint16_t) 0x109)
#define PPSMC_MSG_Thermal_Cntl_Enable ((uint16_t) 0x10a)
#define PPSMC_MSG_Reset_Service ((uint16_t) 0x10b)
#define PPSMC_MSG_VCEPowerOFF ((uint16_t) 0x10e)
#define PPSMC_MSG_VCEPowerON ((uint16_t) 0x10f)
#define PPSMC_MSG_DPM_Disable_VCE_HS ((uint16_t) 0x110)
#define PPSMC_MSG_DPM_Enable_VCE_HS ((uint16_t) 0x111)
#define PPSMC_MSG_DPM_N_LevelsDisabled ((uint16_t) 0x112)
#define PPSMC_MSG_DCEPowerOFF ((uint16_t) 0x113)
#define PPSMC_MSG_DCEPowerON ((uint16_t) 0x114)
#define PPSMC_MSG_PCIE_DDIPowerDown ((uint16_t) 0x117)
#define PPSMC_MSG_PCIE_DDIPowerUp ((uint16_t) 0x118)
#define PPSMC_MSG_PCIE_CascadePLLPowerDown ((uint16_t) 0x119)
#define PPSMC_MSG_PCIE_CascadePLLPowerUp ((uint16_t) 0x11a)
#define PPSMC_MSG_SYSPLLPowerOff ((uint16_t) 0x11b)
#define PPSMC_MSG_SYSPLLPowerOn ((uint16_t) 0x11c)
#define PPSMC_MSG_DCE_RemoveVoltageAdjustment ((uint16_t) 0x11d)
#define PPSMC_MSG_DCE_AllowVoltageAdjustment ((uint16_t) 0x11e)
#define PPSMC_MSG_DISPLAYPHYStatusNotify ((uint16_t) 0x11f)
#define PPSMC_MSG_EnableBAPM ((uint16_t) 0x120)
#define PPSMC_MSG_DisableBAPM ((uint16_t) 0x121)
#define PPSMC_MSG_PCIE_PHYPowerDown ((uint16_t) 0x122)
#define PPSMC_MSG_PCIE_PHYPowerUp ((uint16_t) 0x123)
#define PPSMC_MSG_UVD_DPM_Config ((uint16_t) 0x124)
#define PPSMC_MSG_Spmi_Enable ((uint16_t) 0x122)
#define PPSMC_MSG_Spmi_Timer ((uint16_t) 0x123)
#define PPSMC_MSG_LCLK_DPM_Config ((uint16_t) 0x124)
#define PPSMC_MSG_NBDPM_Config ((uint16_t) 0x125)
#define PPSMC_MSG_PCIE_DDIPhyPowerDown ((uint16_t) 0x126)
#define PPSMC_MSG_PCIE_DDIPhyPowerUp ((uint16_t) 0x127)
#define PPSMC_MSG_MCLKDPM_Config ((uint16_t) 0x128)
#define PPSMC_MSG_UVDDPM_Config ((uint16_t) 0x129)
#define PPSMC_MSG_VCEDPM_Config ((uint16_t) 0x12A)
#define PPSMC_MSG_ACPDPM_Config ((uint16_t) 0x12B)
#define PPSMC_MSG_SAMUDPM_Config ((uint16_t) 0x12C)
#define PPSMC_MSG_UVDDPM_SetEnabledMask ((uint16_t) 0x12D)
#define PPSMC_MSG_VCEDPM_SetEnabledMask ((uint16_t) 0x12E)
#define PPSMC_MSG_ACPDPM_SetEnabledMask ((uint16_t) 0x12F)
#define PPSMC_MSG_SAMUDPM_SetEnabledMask ((uint16_t) 0x130)
#define PPSMC_MSG_MCLKDPM_ForceState ((uint16_t) 0x131)
#define PPSMC_MSG_MCLKDPM_NoForcedLevel ((uint16_t) 0x132)
#define PPSMC_MSG_Thermal_Cntl_Disable ((uint16_t) 0x133)
#define PPSMC_MSG_SetTDPLimit ((uint16_t) 0x134)
#define PPSMC_MSG_Voltage_Cntl_Disable ((uint16_t) 0x135)
#define PPSMC_MSG_PCIeDPM_Enable ((uint16_t) 0x136)
#define PPSMC_MSG_ACPPowerOFF ((uint16_t) 0x137)
#define PPSMC_MSG_ACPPowerON ((uint16_t) 0x138)
#define PPSMC_MSG_SAMPowerOFF ((uint16_t) 0x139)
#define PPSMC_MSG_SAMPowerON ((uint16_t) 0x13a)
#define PPSMC_MSG_SDMAPowerOFF ((uint16_t) 0x13b)
#define PPSMC_MSG_SDMAPowerON ((uint16_t) 0x13c)
#define PPSMC_MSG_PCIeDPM_Disable ((uint16_t) 0x13d)
#define PPSMC_MSG_IOMMUPowerOFF ((uint16_t) 0x13e)
#define PPSMC_MSG_IOMMUPowerON ((uint16_t) 0x13f)
#define PPSMC_MSG_NBDPM_Enable ((uint16_t) 0x140)
#define PPSMC_MSG_NBDPM_Disable ((uint16_t) 0x141)
#define PPSMC_MSG_NBDPM_ForceNominal ((uint16_t) 0x142)
#define PPSMC_MSG_NBDPM_ForcePerformance ((uint16_t) 0x143)
#define PPSMC_MSG_NBDPM_UnForce ((uint16_t) 0x144)
#define PPSMC_MSG_SCLKDPM_SetEnabledMask ((uint16_t) 0x145)
#define PPSMC_MSG_MCLKDPM_SetEnabledMask ((uint16_t) 0x146)
#define PPSMC_MSG_PCIeDPM_ForceLevel ((uint16_t) 0x147)
#define PPSMC_MSG_PCIeDPM_UnForceLevel ((uint16_t) 0x148)
#define PPSMC_MSG_EnableACDCGPIOInterrupt ((uint16_t) 0x149)
#define PPSMC_MSG_EnableVRHotGPIOInterrupt ((uint16_t) 0x14a)
#define PPSMC_MSG_SwitchToAC ((uint16_t) 0x14b)
#define PPSMC_MSG_XDMAPowerOFF ((uint16_t) 0x14c)
#define PPSMC_MSG_XDMAPowerON ((uint16_t) 0x14d)
#define PPSMC_MSG_DPM_Enable ((uint16_t)0x14e)
#define PPSMC_MSG_DPM_Disable ((uint16_t)0x14f)
#define PPSMC_MSG_MCLKDPM_Enable ((uint16_t)0x150)
#define PPSMC_MSG_MCLKDPM_Disable ((uint16_t)0x151)
#define PPSMC_MSG_LCLKDPM_Enable ((uint16_t)0x152)
#define PPSMC_MSG_LCLKDPM_Disable ((uint16_t)0x153)
#define PPSMC_MSG_UVDDPM_Enable ((uint16_t)0x154)
#define PPSMC_MSG_UVDDPM_Disable ((uint16_t)0x155)
#define PPSMC_MSG_SAMUDPM_Enable ((uint16_t)0x156)
#define PPSMC_MSG_SAMUDPM_Disable ((uint16_t)0x157)
#define PPSMC_MSG_ACPDPM_Enable ((uint16_t)0x158)
#define PPSMC_MSG_ACPDPM_Disable ((uint16_t)0x159)
#define PPSMC_MSG_VCEDPM_Enable ((uint16_t)0x15a)
#define PPSMC_MSG_VCEDPM_Disable ((uint16_t)0x15b)
#define PPSMC_MSG_LCLKDPM_SetEnabledMask ((uint16_t)0x15c)
#define PPSMC_MSG_DPM_FPS_Mode ((uint16_t) 0x15d)
#define PPSMC_MSG_DPM_Activity_Mode ((uint16_t) 0x15e)
#define PPSMC_MSG_VddC_Request ((uint16_t) 0x15f)
#define PPSMC_MSG_MCLKDPM_GetEnabledMask ((uint16_t) 0x160)
#define PPSMC_MSG_LCLKDPM_GetEnabledMask ((uint16_t) 0x161)
#define PPSMC_MSG_SCLKDPM_GetEnabledMask ((uint16_t) 0x162)
#define PPSMC_MSG_UVDDPM_GetEnabledMask ((uint16_t) 0x163)
#define PPSMC_MSG_SAMUDPM_GetEnabledMask ((uint16_t) 0x164)
#define PPSMC_MSG_ACPDPM_GetEnabledMask ((uint16_t) 0x165)
#define PPSMC_MSG_VCEDPM_GetEnabledMask ((uint16_t) 0x166)
#define PPSMC_MSG_PCIeDPM_SetEnabledMask ((uint16_t) 0x167)
#define PPSMC_MSG_PCIeDPM_GetEnabledMask ((uint16_t) 0x168)
#define PPSMC_MSG_TDCLimitEnable ((uint16_t) 0x169)
#define PPSMC_MSG_TDCLimitDisable ((uint16_t) 0x16a)
#define PPSMC_MSG_DPM_AutoRotate_Mode ((uint16_t) 0x16b)
#define PPSMC_MSG_DISPCLK_FROM_FCH ((uint16_t)0x16c)
#define PPSMC_MSG_DISPCLK_FROM_DFS ((uint16_t)0x16d)
#define PPSMC_MSG_DPREFCLK_FROM_FCH ((uint16_t)0x16e)
#define PPSMC_MSG_DPREFCLK_FROM_DFS ((uint16_t)0x16f)
#define PPSMC_MSG_PmStatusLogStart ((uint16_t)0x170)
#define PPSMC_MSG_PmStatusLogSample ((uint16_t)0x171)
#define PPSMC_MSG_SCLK_AutoDPM_ON ((uint16_t) 0x172)
#define PPSMC_MSG_MCLK_AutoDPM_ON ((uint16_t) 0x173)
#define PPSMC_MSG_LCLK_AutoDPM_ON ((uint16_t) 0x174)
#define PPSMC_MSG_UVD_AutoDPM_ON ((uint16_t) 0x175)
#define PPSMC_MSG_SAMU_AutoDPM_ON ((uint16_t) 0x176)
#define PPSMC_MSG_ACP_AutoDPM_ON ((uint16_t) 0x177)
#define PPSMC_MSG_VCE_AutoDPM_ON ((uint16_t) 0x178)
#define PPSMC_MSG_PCIe_AutoDPM_ON ((uint16_t) 0x179)
#define PPSMC_MSG_MASTER_AutoDPM_ON ((uint16_t) 0x17a)
#define PPSMC_MSG_MASTER_AutoDPM_OFF ((uint16_t) 0x17b)
#define PPSMC_MSG_DYNAMICDISPPHYPOWER ((uint16_t) 0x17c)
#define PPSMC_MSG_CAC_COLLECTION_ON ((uint16_t) 0x17d)
#define PPSMC_MSG_CAC_COLLECTION_OFF ((uint16_t) 0x17e)
#define PPSMC_MSG_CAC_CORRELATION_ON ((uint16_t) 0x17f)
#define PPSMC_MSG_CAC_CORRELATION_OFF ((uint16_t) 0x180)
#define PPSMC_MSG_PM_STATUS_TO_DRAM_ON ((uint16_t) 0x181)
#define PPSMC_MSG_PM_STATUS_TO_DRAM_OFF ((uint16_t) 0x182)
#define PPSMC_MSG_UVD_HANDSHAKE_OFF ((uint16_t) 0x183)
#define PPSMC_MSG_ALLOW_LOWSCLK_INTERRUPT ((uint16_t) 0x184)
#define PPSMC_MSG_PkgPwrLimitEnable ((uint16_t) 0x185)
#define PPSMC_MSG_PkgPwrLimitDisable ((uint16_t) 0x186)
#define PPSMC_MSG_PkgPwrSetLimit ((uint16_t) 0x187)
#define PPSMC_MSG_OverDriveSetTargetTdp ((uint16_t) 0x188)
#define PPSMC_MSG_SCLKDPM_FreezeLevel ((uint16_t) 0x189)
#define PPSMC_MSG_SCLKDPM_UnfreezeLevel ((uint16_t) 0x18A)
#define PPSMC_MSG_MCLKDPM_FreezeLevel ((uint16_t) 0x18B)
#define PPSMC_MSG_MCLKDPM_UnfreezeLevel ((uint16_t) 0x18C)
#define PPSMC_MSG_START_DRAM_LOGGING ((uint16_t) 0x18D)
#define PPSMC_MSG_STOP_DRAM_LOGGING ((uint16_t) 0x18E)
#define PPSMC_MSG_MASTER_DeepSleep_ON ((uint16_t) 0x18F)
#define PPSMC_MSG_MASTER_DeepSleep_OFF ((uint16_t) 0x190)
#define PPSMC_MSG_Remove_DC_Clamp ((uint16_t) 0x191)
#define PPSMC_MSG_DisableACDCGPIOInterrupt ((uint16_t) 0x192)
#define PPSMC_MSG_OverrideVoltageControl_SetVddc ((uint16_t) 0x193)
#define PPSMC_MSG_OverrideVoltageControl_SetVddci ((uint16_t) 0x194)
#define PPSMC_MSG_SetVidOffset_1 ((uint16_t) 0x195)
#define PPSMC_MSG_SetVidOffset_2 ((uint16_t) 0x207)
#define PPSMC_MSG_GetVidOffset_1 ((uint16_t) 0x196)
#define PPSMC_MSG_GetVidOffset_2 ((uint16_t) 0x208)
#define PPSMC_MSG_THERMAL_OVERDRIVE_Enable ((uint16_t) 0x197)
#define PPSMC_MSG_THERMAL_OVERDRIVE_Disable ((uint16_t) 0x198)
#define PPSMC_MSG_SetTjMax ((uint16_t) 0x199)
#define PPSMC_MSG_SetFanPwmMax ((uint16_t) 0x19A)
#define PPSMC_MSG_WaitForMclkSwitchFinish ((uint16_t) 0x19B)
#define PPSMC_MSG_ENABLE_THERMAL_DPM ((uint16_t) 0x19C)
#define PPSMC_MSG_DISABLE_THERMAL_DPM ((uint16_t) 0x19D)
#define PPSMC_MSG_Enable_PCC ((uint16_t) 0x19E)
#define PPSMC_MSG_Disable_PCC ((uint16_t) 0x19F)
#define PPSMC_MSG_API_GetSclkFrequency ((uint16_t) 0x200)
#define PPSMC_MSG_API_GetMclkFrequency ((uint16_t) 0x201)
#define PPSMC_MSG_API_GetSclkBusy ((uint16_t) 0x202)
#define PPSMC_MSG_API_GetMclkBusy ((uint16_t) 0x203)
#define PPSMC_MSG_API_GetAsicPower ((uint16_t) 0x204)
#define PPSMC_MSG_SetFanRpmMax ((uint16_t) 0x205)
#define PPSMC_MSG_SetFanSclkTarget ((uint16_t) 0x206)
#define PPSMC_MSG_SetFanMinPwm ((uint16_t) 0x209)
#define PPSMC_MSG_SetFanTemperatureTarget ((uint16_t) 0x20A)
#define PPSMC_MSG_BACO_StartMonitor ((uint16_t) 0x240)
#define PPSMC_MSG_BACO_Cancel ((uint16_t) 0x241)
#define PPSMC_MSG_EnableVddGfx ((uint16_t) 0x242)
#define PPSMC_MSG_DisableVddGfx ((uint16_t) 0x243)
#define PPSMC_MSG_UcodeAddressLow ((uint16_t) 0x244)
#define PPSMC_MSG_UcodeAddressHigh ((uint16_t) 0x245)
#define PPSMC_MSG_UcodeLoadStatus ((uint16_t) 0x246)
#define PPSMC_MSG_DRV_DRAM_ADDR_HI ((uint16_t) 0x250)
#define PPSMC_MSG_DRV_DRAM_ADDR_LO ((uint16_t) 0x251)
#define PPSMC_MSG_SMU_DRAM_ADDR_HI ((uint16_t) 0x252)
#define PPSMC_MSG_SMU_DRAM_ADDR_LO ((uint16_t) 0x253)
#define PPSMC_MSG_LoadUcodes ((uint16_t) 0x254)
#define PPSMC_MSG_PowerStateNotify ((uint16_t) 0x255)
#define PPSMC_MSG_COND_EXEC_DRAM_ADDR_HI ((uint16_t) 0x256)
#define PPSMC_MSG_COND_EXEC_DRAM_ADDR_LO ((uint16_t) 0x257)
#define PPSMC_MSG_VBIOS_DRAM_ADDR_HI ((uint16_t) 0x258)
#define PPSMC_MSG_VBIOS_DRAM_ADDR_LO ((uint16_t) 0x259)
#define PPSMC_MSG_LoadVBios ((uint16_t) 0x25A)
#define PPSMC_MSG_GetUcodeVersion ((uint16_t) 0x25B)
#define DMCUSMC_MSG_PSREntry ((uint16_t) 0x25C)
#define DMCUSMC_MSG_PSRExit ((uint16_t) 0x25D)
#define PPSMC_MSG_EnableClockGatingFeature ((uint16_t) 0x260)
#define PPSMC_MSG_DisableClockGatingFeature ((uint16_t) 0x261)
#define PPSMC_MSG_IsDeviceRunning ((uint16_t) 0x262)
#define PPSMC_MSG_LoadMetaData ((uint16_t) 0x263)
#define PPSMC_MSG_TMON_AutoCaliberate_Enable ((uint16_t) 0x264)
#define PPSMC_MSG_TMON_AutoCaliberate_Disable ((uint16_t) 0x265)
#define PPSMC_MSG_GetTelemetry1Slope ((uint16_t) 0x266)
#define PPSMC_MSG_GetTelemetry1Offset ((uint16_t) 0x267)
#define PPSMC_MSG_GetTelemetry2Slope ((uint16_t) 0x268)
#define PPSMC_MSG_GetTelemetry2Offset ((uint16_t) 0x269)
typedef uint16_t PPSMC_Msg;
/* If the SMC firmware has an event status soft register this is what the individual bits mean.*/
#define PPSMC_EVENT_STATUS_THERMAL 0x00000001
#define PPSMC_EVENT_STATUS_REGULATORHOT 0x00000002
#define PPSMC_EVENT_STATUS_DC 0x00000004
#define PPSMC_EVENT_STATUS_GPIO17 0x00000008
#pragma pack(pop)
#endif