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pinctrl: renesas: rzg2l: Make reverse order of enable() for disable()
[ Upstream commitdd462cf53e
] We usually do reverse order of enable() for disable(). Currently, the ordering of irq_chip_disable_parent() is not correct in rzg2l_gpio_irq_disable(). Fix the incorrect order. Fixes:db2e5f21a4
("pinctrl: renesas: pinctrl-rzg2l: Add IRQ domain to handle GPIO interrupt") Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Tested-by: Claudiu Beznea <claudiu.beznea.uj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/r/20230918123355.262115-2-biju.das.jz@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Sasha Levin <sashal@kernel.org>
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@ -1175,6 +1175,8 @@ static void rzg2l_gpio_irq_disable(struct irq_data *d)
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u32 port;
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u8 bit;
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irq_chip_disable_parent(d);
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port = RZG2L_PIN_ID_TO_PORT(hwirq);
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bit = RZG2L_PIN_ID_TO_PIN(hwirq);
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@ -1189,7 +1191,6 @@ static void rzg2l_gpio_irq_disable(struct irq_data *d)
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spin_unlock_irqrestore(&pctrl->lock, flags);
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gpiochip_disable_irq(gc, hwirq);
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irq_chip_disable_parent(d);
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}
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static void rzg2l_gpio_irq_enable(struct irq_data *d)
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