korg/linux
0
0
Fork 0
mirror of https://mirrors.bfsu.edu.cn/git/linux.git synced 2025-01-10 15:54:39 +08:00
Code Issues Packages Projects Releases Wiki Activity

[PATCH] x86: when L3 is present show its size in /proc/cpuinfo

Browse Source 
The code that prints the cache size assumes that L3 always lives in chipset
and is shared across CPUs.  Which is not really true.

I think all the cachesizes reported by cpuid are in the processor itself.
The attached patch changes the code to reflect that.

Signed-off-by: Venkatesh Pallipadi <venkatesh.pallipadi@intel.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This commit is contained in:
Venkatesh Pallipadi 2005-10-30 14:59:38 -08:00 committed by Linus Torvalds
parent f014a556e7
commit 30037f66ce
1 changed files with 1 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
arch/i386/kernel/cpu/intel_cacheinfo.c
View File

@ -278,13 +278,7 @@ unsigned int __devinit init_intel_cacheinfo(struct cpuinfo_x86 *c)
if ( l3 ) if ( l3 )
printk(KERN_INFO "CPU: L3 cache: %dK\n", l3); printk(KERN_INFO "CPU: L3 cache: %dK\n", l3);
/* c->x86_cache_size = l3 ? l3 : (l2 ? l2 : (l1i+l1d));
* This assumes the L3 cache is shared; it typically lives in
* the northbridge. The L1 caches are included by the L2
* cache, and so should not be included for the purpose of
* SMP switching weights.
*/
c->x86_cache_size = l2 ? l2 : (l1i+l1d);
} }
return l2; return l2;