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cxgb4vf: Fix sparse warnings
Fixes sparse warnings introduced in commite85c9a7abf
("cxgb4/cxgb4vf: Add code to calculate T5 BAR2 Offsets for SGE Queue Registers") anddf64e4d38c
("cxgb4/cxgb4vf: Use new interfaces to calculate BAR2 SGE Queue Register addresses") and few old ones sparse warnings: >> drivers/net/ethernet/chelsio/cxgb4vf/sge.c:1006:48: sparse: cast removes >> address space of expression >> drivers/net/ethernet/chelsio/cxgb4vf/sge.c:1006:48: sparse: incorrect type in >> initializer (different address space) >> drivers/net/ethernet/chelsio/cxgb4vf/sge.c:1020:40: sparse: incorrect type in >> argument 1 (different base types) Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Hariprasad Shenai <hariprasad@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
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@ -1004,7 +1004,7 @@ static inline void ring_tx_db(struct adapter *adapter, struct sge_txq *tq,
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? (tq->pidx - 1)
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: (tq->size - 1));
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__be64 *src = (__be64 *)&tq->desc[index];
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__be64 __iomem *dst = (__be64 *)(tq->bar2_addr +
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__be64 __iomem *dst = (__be64 __iomem *)(tq->bar2_addr +
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SGE_UDB_WCDOORBELL);
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unsigned int count = EQ_UNIT / sizeof(__be64);
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@ -1018,7 +1018,11 @@ static inline void ring_tx_db(struct adapter *adapter, struct sge_txq *tq,
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* DMA.
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*/
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while (count) {
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writeq(*src, dst);
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/* the (__force u64) is because the compiler
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* doesn't understand the endian swizzling
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* going on
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*/
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writeq((__force u64)*src, dst);
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src++;
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dst++;
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count--;
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@ -1252,8 +1256,8 @@ int t4vf_eth_xmit(struct sk_buff *skb, struct net_device *dev)
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BUG_ON(DIV_ROUND_UP(ETHTXQ_MAX_HDR, TXD_PER_EQ_UNIT) > 1);
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wr = (void *)&txq->q.desc[txq->q.pidx];
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wr->equiq_to_len16 = cpu_to_be32(wr_mid);
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wr->r3[0] = cpu_to_be64(0);
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wr->r3[1] = cpu_to_be64(0);
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wr->r3[0] = cpu_to_be32(0);
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wr->r3[1] = cpu_to_be32(0);
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skb_copy_from_linear_data(skb, (void *)wr->ethmacdst, fw_hdr_copy_len);
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end = (u64 *)wr + flits;
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@ -210,10 +210,10 @@ int t4vf_wr_mbox_core(struct adapter *adapter, const void *cmd, int size,
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if (rpl) {
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/* request bit in high-order BE word */
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WARN_ON((be32_to_cpu(*(const u32 *)cmd)
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WARN_ON((be32_to_cpu(*(const __be32 *)cmd)
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& FW_CMD_REQUEST_F) == 0);
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get_mbox_rpl(adapter, rpl, size, mbox_data);
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WARN_ON((be32_to_cpu(*(u32 *)rpl)
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WARN_ON((be32_to_cpu(*(__be32 *)rpl)
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& FW_CMD_REQUEST_F) != 0);
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}
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t4_write_reg(adapter, mbox_ctl,
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@ -484,7 +484,7 @@ int t4_bar2_sge_qregs(struct adapter *adapter,
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* o The BAR2 Queue ID.
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* o The BAR2 Queue ID Offset into the BAR2 page.
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*/
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bar2_page_offset = ((qid >> qpp_shift) << page_shift);
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bar2_page_offset = ((u64)(qid >> qpp_shift) << page_shift);
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bar2_qid = qid & qpp_mask;
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bar2_qid_offset = bar2_qid * SGE_UDB_SIZE;
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