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arm64: entry: organise entry handlers consistently
In entry.S we have two comments which distinguish EL0 and EL1 exception handlers, but the code isn't actually laid out to match, and there are a few other inconsistencies that would be good to clear up. This patch organizes the entry handers consistently: * The handlers are laid out in order of the vectors, to make them easier to navigate. * The inconsistently-applied alignment is removed * The handlers are consistently marked with SYM_CODE_START_LOCAL() rather than SYM_CODE_START_LOCAL_NOALIGN(), giving them the same default alignment as other assembly code snippets. There should be no functional change as a result of this patch. Signed-off-by: Mark Rutland <mark.rutland@arm.com> Acked-by: Catalin Marinas <catalin.marinas@arm.com> Acked-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Joey Gouly <joey.gouly@arm.com> Cc: James Morse <james.morse@arm.com> Cc: Will Deacon <will@kernel.org> Link: https://lore.kernel.org/r/20210607094624.34689-9-mark.rutland@arm.com Signed-off-by: Will Deacon <will@kernel.org>
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@ -607,87 +607,27 @@ SYM_CODE_END(el1_error_invalid)
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/*
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* EL1 mode handlers.
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*/
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.align 6
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SYM_CODE_START_LOCAL_NOALIGN(el1_sync)
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SYM_CODE_START_LOCAL(el1_sync)
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kernel_entry 1
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mov x0, sp
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bl el1_sync_handler
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kernel_exit 1
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SYM_CODE_END(el1_sync)
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.align 6
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SYM_CODE_START_LOCAL_NOALIGN(el1_irq)
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SYM_CODE_START_LOCAL(el1_irq)
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kernel_entry 1
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mov x0, sp
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bl el1_irq_handler
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kernel_exit 1
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SYM_CODE_END(el1_irq)
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SYM_CODE_START_LOCAL_NOALIGN(el1_fiq)
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SYM_CODE_START_LOCAL(el1_fiq)
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kernel_entry 1
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mov x0, sp
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bl el1_fiq_handler
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kernel_exit 1
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SYM_CODE_END(el1_fiq)
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/*
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* EL0 mode handlers.
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*/
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.align 6
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SYM_CODE_START_LOCAL_NOALIGN(el0_sync)
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kernel_entry 0
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mov x0, sp
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bl el0_sync_handler
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b ret_to_user
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SYM_CODE_END(el0_sync)
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#ifdef CONFIG_COMPAT
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.align 6
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SYM_CODE_START_LOCAL_NOALIGN(el0_sync_compat)
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kernel_entry 0, 32
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mov x0, sp
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bl el0_sync_compat_handler
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b ret_to_user
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SYM_CODE_END(el0_sync_compat)
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.align 6
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SYM_CODE_START_LOCAL_NOALIGN(el0_irq_compat)
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kernel_entry 0, 32
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mov x0, sp
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bl el0_irq_compat_handler
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b ret_to_user
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SYM_CODE_END(el0_irq_compat)
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SYM_CODE_START_LOCAL_NOALIGN(el0_fiq_compat)
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kernel_entry 0, 32
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mov x0, sp
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bl el0_fiq_compat_handler
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b ret_to_user
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SYM_CODE_END(el0_fiq_compat)
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SYM_CODE_START_LOCAL_NOALIGN(el0_error_compat)
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kernel_entry 0, 32
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mov x0, sp
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bl el0_error_compat_handler
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b ret_to_user
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SYM_CODE_END(el0_error_compat)
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#endif
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.align 6
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SYM_CODE_START_LOCAL_NOALIGN(el0_irq)
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kernel_entry 0
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mov x0, sp
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bl el0_irq_handler
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b ret_to_user
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SYM_CODE_END(el0_irq)
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SYM_CODE_START_LOCAL_NOALIGN(el0_fiq)
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kernel_entry 0
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mov x0, sp
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bl el0_fiq_handler
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b ret_to_user
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SYM_CODE_END(el0_fiq)
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SYM_CODE_START_LOCAL(el1_error)
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kernel_entry 1
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mov x0, sp
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@ -695,6 +635,30 @@ SYM_CODE_START_LOCAL(el1_error)
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kernel_exit 1
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SYM_CODE_END(el1_error)
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/*
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* EL0 mode handlers.
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*/
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SYM_CODE_START_LOCAL(el0_sync)
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kernel_entry 0
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mov x0, sp
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bl el0_sync_handler
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b ret_to_user
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SYM_CODE_END(el0_sync)
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SYM_CODE_START_LOCAL(el0_irq)
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kernel_entry 0
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mov x0, sp
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bl el0_irq_handler
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b ret_to_user
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SYM_CODE_END(el0_irq)
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SYM_CODE_START_LOCAL(el0_fiq)
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kernel_entry 0
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mov x0, sp
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bl el0_fiq_handler
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b ret_to_user
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SYM_CODE_END(el0_fiq)
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SYM_CODE_START_LOCAL(el0_error)
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kernel_entry 0
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mov x0, sp
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@ -702,6 +666,36 @@ SYM_CODE_START_LOCAL(el0_error)
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b ret_to_user
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SYM_CODE_END(el0_error)
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#ifdef CONFIG_COMPAT
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SYM_CODE_START_LOCAL(el0_sync_compat)
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kernel_entry 0, 32
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mov x0, sp
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bl el0_sync_compat_handler
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b ret_to_user
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SYM_CODE_END(el0_sync_compat)
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SYM_CODE_START_LOCAL(el0_irq_compat)
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kernel_entry 0, 32
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mov x0, sp
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bl el0_irq_compat_handler
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b ret_to_user
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SYM_CODE_END(el0_irq_compat)
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SYM_CODE_START_LOCAL(el0_fiq_compat)
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kernel_entry 0, 32
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mov x0, sp
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bl el0_fiq_compat_handler
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b ret_to_user
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SYM_CODE_END(el0_fiq_compat)
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SYM_CODE_START_LOCAL(el0_error_compat)
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kernel_entry 0, 32
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mov x0, sp
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bl el0_error_compat_handler
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b ret_to_user
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SYM_CODE_END(el0_error_compat)
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#endif
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/*
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* "slow" syscall return path.
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*/
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