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SERIAL: Lantiq: Add driver for MIPS Lantiq SOCs.
Signed-off-by: John Crispin <blogic@openwrt.org> Signed-off-by: Ralph Hempel <ralph.hempel@lantiq.com> Signed-off-by: Felix Fietkau <nbd@openwrt.org> Cc: alan@lxorguk.ukuu.org.uk Cc: linux-mips@linux-mips.org Cc: linux-serial@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/2269/ Acked-by: Alan Cox <alan@linux.intel.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
John Crispin
Ralf Baechle
parent
935c500c37
commit
2f0fc4159a
@ -1391,6 +1391,14 @@ config SERIAL_OF_PLATFORM_NWPSERIAL_CONSOLE
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help
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Support for Console on the NWP serial ports.
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config SERIAL_LANTIQ
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bool "Lantiq serial driver"
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depends on LANTIQ
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select SERIAL_CORE
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select SERIAL_CORE_CONSOLE
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help
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Support for console and UART on Lantiq SoCs.
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config SERIAL_QE
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tristate "Freescale QUICC Engine serial port support"
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depends on QUICC_ENGINE
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@ -94,3 +94,4 @@ obj-$(CONFIG_SERIAL_IFX6X60) += ifx6x60.o
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obj-$(CONFIG_SERIAL_PCH_UART) += pch_uart.o
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obj-$(CONFIG_SERIAL_MSM_SMD) += msm_smd_tty.o
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obj-$(CONFIG_SERIAL_MXS_AUART) += mxs-auart.o
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obj-$(CONFIG_SERIAL_LANTIQ) += lantiq.o
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756
drivers/tty/serial/lantiq.c
Normal file
756
drivers/tty/serial/lantiq.c
Normal file
@ -0,0 +1,756 @@
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/*
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* Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published
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* by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*
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* Copyright (C) 2004 Infineon IFAP DC COM CPE
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* Copyright (C) 2007 Felix Fietkau <nbd@openwrt.org>
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* Copyright (C) 2007 John Crispin <blogic@openwrt.org>
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* Copyright (C) 2010 Thomas Langer, <thomas.langer@lantiq.com>
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*/
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#include <linux/slab.h>
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#include <linux/module.h>
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#include <linux/ioport.h>
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#include <linux/init.h>
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#include <linux/console.h>
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#include <linux/sysrq.h>
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#include <linux/device.h>
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#include <linux/tty.h>
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#include <linux/tty_flip.h>
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#include <linux/serial_core.h>
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#include <linux/serial.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/clk.h>
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#include <lantiq_soc.h>
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#define PORT_LTQ_ASC 111
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#define MAXPORTS 2
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#define UART_DUMMY_UER_RX 1
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#define DRVNAME "ltq_asc"
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#ifdef __BIG_ENDIAN
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#define LTQ_ASC_TBUF (0x0020 + 3)
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#define LTQ_ASC_RBUF (0x0024 + 3)
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#else
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#define LTQ_ASC_TBUF 0x0020
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#define LTQ_ASC_RBUF 0x0024
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#endif
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#define LTQ_ASC_FSTAT 0x0048
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#define LTQ_ASC_WHBSTATE 0x0018
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#define LTQ_ASC_STATE 0x0014
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#define LTQ_ASC_IRNCR 0x00F8
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#define LTQ_ASC_CLC 0x0000
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#define LTQ_ASC_ID 0x0008
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#define LTQ_ASC_PISEL 0x0004
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#define LTQ_ASC_TXFCON 0x0044
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#define LTQ_ASC_RXFCON 0x0040
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#define LTQ_ASC_CON 0x0010
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#define LTQ_ASC_BG 0x0050
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#define LTQ_ASC_IRNREN 0x00F4
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#define ASC_IRNREN_TX 0x1
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#define ASC_IRNREN_RX 0x2
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#define ASC_IRNREN_ERR 0x4
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#define ASC_IRNREN_TX_BUF 0x8
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#define ASC_IRNCR_TIR 0x1
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#define ASC_IRNCR_RIR 0x2
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#define ASC_IRNCR_EIR 0x4
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#define ASCOPT_CSIZE 0x3
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#define TXFIFO_FL 1
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#define RXFIFO_FL 1
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#define ASCCLC_DISS 0x2
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#define ASCCLC_RMCMASK 0x0000FF00
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#define ASCCLC_RMCOFFSET 8
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#define ASCCON_M_8ASYNC 0x0
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#define ASCCON_M_7ASYNC 0x2
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#define ASCCON_ODD 0x00000020
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#define ASCCON_STP 0x00000080
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#define ASCCON_BRS 0x00000100
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#define ASCCON_FDE 0x00000200
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#define ASCCON_R 0x00008000
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#define ASCCON_FEN 0x00020000
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#define ASCCON_ROEN 0x00080000
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#define ASCCON_TOEN 0x00100000
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#define ASCSTATE_PE 0x00010000
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#define ASCSTATE_FE 0x00020000
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#define ASCSTATE_ROE 0x00080000
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#define ASCSTATE_ANY (ASCSTATE_ROE|ASCSTATE_PE|ASCSTATE_FE)
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#define ASCWHBSTATE_CLRREN 0x00000001
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#define ASCWHBSTATE_SETREN 0x00000002
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#define ASCWHBSTATE_CLRPE 0x00000004
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#define ASCWHBSTATE_CLRFE 0x00000008
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#define ASCWHBSTATE_CLRROE 0x00000020
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#define ASCTXFCON_TXFEN 0x0001
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#define ASCTXFCON_TXFFLU 0x0002
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#define ASCTXFCON_TXFITLMASK 0x3F00
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#define ASCTXFCON_TXFITLOFF 8
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#define ASCRXFCON_RXFEN 0x0001
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#define ASCRXFCON_RXFFLU 0x0002
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#define ASCRXFCON_RXFITLMASK 0x3F00
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#define ASCRXFCON_RXFITLOFF 8
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#define ASCFSTAT_RXFFLMASK 0x003F
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#define ASCFSTAT_TXFFLMASK 0x3F00
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#define ASCFSTAT_TXFREEMASK 0x3F000000
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#define ASCFSTAT_TXFREEOFF 24
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static void lqasc_tx_chars(struct uart_port *port);
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static struct ltq_uart_port *lqasc_port[MAXPORTS];
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static struct uart_driver lqasc_reg;
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static DEFINE_SPINLOCK(ltq_asc_lock);
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struct ltq_uart_port {
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struct uart_port port;
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struct clk *clk;
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unsigned int tx_irq;
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unsigned int rx_irq;
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unsigned int err_irq;
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};
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static inline struct
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ltq_uart_port *to_ltq_uart_port(struct uart_port *port)
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{
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return container_of(port, struct ltq_uart_port, port);
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}
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static void
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lqasc_stop_tx(struct uart_port *port)
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{
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return;
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}
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static void
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lqasc_start_tx(struct uart_port *port)
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{
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unsigned long flags;
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spin_lock_irqsave(<q_asc_lock, flags);
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lqasc_tx_chars(port);
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spin_unlock_irqrestore(<q_asc_lock, flags);
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return;
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}
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static void
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lqasc_stop_rx(struct uart_port *port)
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{
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ltq_w32(ASCWHBSTATE_CLRREN, port->membase + LTQ_ASC_WHBSTATE);
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}
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static void
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lqasc_enable_ms(struct uart_port *port)
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{
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}
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static int
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lqasc_rx_chars(struct uart_port *port)
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{
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struct tty_struct *tty = tty_port_tty_get(&port->state->port);
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unsigned int ch = 0, rsr = 0, fifocnt;
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if (!tty) {
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dev_dbg(port->dev, "%s:tty is busy now", __func__);
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return -EBUSY;
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}
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fifocnt =
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ltq_r32(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_RXFFLMASK;
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while (fifocnt--) {
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u8 flag = TTY_NORMAL;
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ch = ltq_r8(port->membase + LTQ_ASC_RBUF);
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rsr = (ltq_r32(port->membase + LTQ_ASC_STATE)
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& ASCSTATE_ANY) | UART_DUMMY_UER_RX;
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tty_flip_buffer_push(tty);
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port->icount.rx++;
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/*
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* Note that the error handling code is
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* out of the main execution path
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*/
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if (rsr & ASCSTATE_ANY) {
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if (rsr & ASCSTATE_PE) {
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port->icount.parity++;
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ltq_w32_mask(0, ASCWHBSTATE_CLRPE,
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port->membase + LTQ_ASC_WHBSTATE);
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} else if (rsr & ASCSTATE_FE) {
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port->icount.frame++;
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ltq_w32_mask(0, ASCWHBSTATE_CLRFE,
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port->membase + LTQ_ASC_WHBSTATE);
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}
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if (rsr & ASCSTATE_ROE) {
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port->icount.overrun++;
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ltq_w32_mask(0, ASCWHBSTATE_CLRROE,
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port->membase + LTQ_ASC_WHBSTATE);
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}
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rsr &= port->read_status_mask;
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if (rsr & ASCSTATE_PE)
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flag = TTY_PARITY;
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else if (rsr & ASCSTATE_FE)
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flag = TTY_FRAME;
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}
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if ((rsr & port->ignore_status_mask) == 0)
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tty_insert_flip_char(tty, ch, flag);
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if (rsr & ASCSTATE_ROE)
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/*
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* Overrun is special, since it's reported
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* immediately, and doesn't affect the current
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* character
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*/
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tty_insert_flip_char(tty, 0, TTY_OVERRUN);
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}
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if (ch != 0)
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tty_flip_buffer_push(tty);
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tty_kref_put(tty);
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return 0;
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}
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static void
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lqasc_tx_chars(struct uart_port *port)
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{
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struct circ_buf *xmit = &port->state->xmit;
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if (uart_tx_stopped(port)) {
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lqasc_stop_tx(port);
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return;
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}
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while (((ltq_r32(port->membase + LTQ_ASC_FSTAT) &
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ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF) != 0) {
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if (port->x_char) {
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ltq_w8(port->x_char, port->membase + LTQ_ASC_TBUF);
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port->icount.tx++;
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port->x_char = 0;
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continue;
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}
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if (uart_circ_empty(xmit))
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break;
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ltq_w8(port->state->xmit.buf[port->state->xmit.tail],
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port->membase + LTQ_ASC_TBUF);
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xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
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port->icount.tx++;
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}
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if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
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uart_write_wakeup(port);
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}
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static irqreturn_t
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lqasc_tx_int(int irq, void *_port)
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{
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unsigned long flags;
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struct uart_port *port = (struct uart_port *)_port;
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spin_lock_irqsave(<q_asc_lock, flags);
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ltq_w32(ASC_IRNCR_TIR, port->membase + LTQ_ASC_IRNCR);
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spin_unlock_irqrestore(<q_asc_lock, flags);
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lqasc_start_tx(port);
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return IRQ_HANDLED;
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}
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static irqreturn_t
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lqasc_err_int(int irq, void *_port)
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{
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unsigned long flags;
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struct uart_port *port = (struct uart_port *)_port;
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spin_lock_irqsave(<q_asc_lock, flags);
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/* clear any pending interrupts */
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ltq_w32_mask(0, ASCWHBSTATE_CLRPE | ASCWHBSTATE_CLRFE |
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ASCWHBSTATE_CLRROE, port->membase + LTQ_ASC_WHBSTATE);
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spin_unlock_irqrestore(<q_asc_lock, flags);
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return IRQ_HANDLED;
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}
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static irqreturn_t
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lqasc_rx_int(int irq, void *_port)
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{
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unsigned long flags;
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struct uart_port *port = (struct uart_port *)_port;
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spin_lock_irqsave(<q_asc_lock, flags);
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ltq_w32(ASC_IRNCR_RIR, port->membase + LTQ_ASC_IRNCR);
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lqasc_rx_chars(port);
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spin_unlock_irqrestore(<q_asc_lock, flags);
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return IRQ_HANDLED;
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}
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static unsigned int
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lqasc_tx_empty(struct uart_port *port)
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{
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int status;
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status = ltq_r32(port->membase + LTQ_ASC_FSTAT) & ASCFSTAT_TXFFLMASK;
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return status ? 0 : TIOCSER_TEMT;
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}
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static unsigned int
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lqasc_get_mctrl(struct uart_port *port)
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{
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return TIOCM_CTS | TIOCM_CAR | TIOCM_DSR;
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}
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static void
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lqasc_set_mctrl(struct uart_port *port, u_int mctrl)
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{
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}
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static void
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lqasc_break_ctl(struct uart_port *port, int break_state)
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{
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}
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static int
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lqasc_startup(struct uart_port *port)
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{
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struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
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int retval;
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port->uartclk = clk_get_rate(ltq_port->clk);
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ltq_w32_mask(ASCCLC_DISS | ASCCLC_RMCMASK, (1 << ASCCLC_RMCOFFSET),
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port->membase + LTQ_ASC_CLC);
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ltq_w32(0, port->membase + LTQ_ASC_PISEL);
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ltq_w32(
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((TXFIFO_FL << ASCTXFCON_TXFITLOFF) & ASCTXFCON_TXFITLMASK) |
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ASCTXFCON_TXFEN | ASCTXFCON_TXFFLU,
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port->membase + LTQ_ASC_TXFCON);
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ltq_w32(
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((RXFIFO_FL << ASCRXFCON_RXFITLOFF) & ASCRXFCON_RXFITLMASK)
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| ASCRXFCON_RXFEN | ASCRXFCON_RXFFLU,
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port->membase + LTQ_ASC_RXFCON);
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/* make sure other settings are written to hardware before
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* setting enable bits
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*/
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wmb();
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ltq_w32_mask(0, ASCCON_M_8ASYNC | ASCCON_FEN | ASCCON_TOEN |
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ASCCON_ROEN, port->membase + LTQ_ASC_CON);
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retval = request_irq(ltq_port->tx_irq, lqasc_tx_int,
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IRQF_DISABLED, "asc_tx", port);
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if (retval) {
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pr_err("failed to request lqasc_tx_int\n");
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return retval;
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}
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retval = request_irq(ltq_port->rx_irq, lqasc_rx_int,
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IRQF_DISABLED, "asc_rx", port);
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if (retval) {
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pr_err("failed to request lqasc_rx_int\n");
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goto err1;
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}
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retval = request_irq(ltq_port->err_irq, lqasc_err_int,
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IRQF_DISABLED, "asc_err", port);
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if (retval) {
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pr_err("failed to request lqasc_err_int\n");
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goto err2;
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}
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ltq_w32(ASC_IRNREN_RX | ASC_IRNREN_ERR | ASC_IRNREN_TX,
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port->membase + LTQ_ASC_IRNREN);
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return 0;
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err2:
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free_irq(ltq_port->rx_irq, port);
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err1:
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free_irq(ltq_port->tx_irq, port);
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return retval;
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}
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static void
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lqasc_shutdown(struct uart_port *port)
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{
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struct ltq_uart_port *ltq_port = to_ltq_uart_port(port);
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free_irq(ltq_port->tx_irq, port);
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free_irq(ltq_port->rx_irq, port);
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free_irq(ltq_port->err_irq, port);
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ltq_w32(0, port->membase + LTQ_ASC_CON);
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ltq_w32_mask(ASCRXFCON_RXFEN, ASCRXFCON_RXFFLU,
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port->membase + LTQ_ASC_RXFCON);
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ltq_w32_mask(ASCTXFCON_TXFEN, ASCTXFCON_TXFFLU,
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port->membase + LTQ_ASC_TXFCON);
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}
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static void
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lqasc_set_termios(struct uart_port *port,
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struct ktermios *new, struct ktermios *old)
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{
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unsigned int cflag;
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unsigned int iflag;
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unsigned int divisor;
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unsigned int baud;
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unsigned int con = 0;
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unsigned long flags;
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cflag = new->c_cflag;
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iflag = new->c_iflag;
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switch (cflag & CSIZE) {
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case CS7:
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con = ASCCON_M_7ASYNC;
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break;
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case CS5:
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case CS6:
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default:
|
||||
new->c_cflag &= ~ CSIZE;
|
||||
new->c_cflag |= CS8;
|
||||
con = ASCCON_M_8ASYNC;
|
||||
break;
|
||||
}
|
||||
|
||||
cflag &= ~CMSPAR; /* Mark/Space parity is not supported */
|
||||
|
||||
if (cflag & CSTOPB)
|
||||
con |= ASCCON_STP;
|
||||
|
||||
if (cflag & PARENB) {
|
||||
if (!(cflag & PARODD))
|
||||
con &= ~ASCCON_ODD;
|
||||
else
|
||||
con |= ASCCON_ODD;
|
||||
}
|
||||
|
||||
port->read_status_mask = ASCSTATE_ROE;
|
||||
if (iflag & INPCK)
|
||||
port->read_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
|
||||
|
||||
port->ignore_status_mask = 0;
|
||||
if (iflag & IGNPAR)
|
||||
port->ignore_status_mask |= ASCSTATE_FE | ASCSTATE_PE;
|
||||
|
||||
if (iflag & IGNBRK) {
|
||||
/*
|
||||
* If we're ignoring parity and break indicators,
|
||||
* ignore overruns too (for real raw support).
|
||||
*/
|
||||
if (iflag & IGNPAR)
|
||||
port->ignore_status_mask |= ASCSTATE_ROE;
|
||||
}
|
||||
|
||||
if ((cflag & CREAD) == 0)
|
||||
port->ignore_status_mask |= UART_DUMMY_UER_RX;
|
||||
|
||||
/* set error signals - framing, parity and overrun, enable receiver */
|
||||
con |= ASCCON_FEN | ASCCON_TOEN | ASCCON_ROEN;
|
||||
|
||||
spin_lock_irqsave(<q_asc_lock, flags);
|
||||
|
||||
/* set up CON */
|
||||
ltq_w32_mask(0, con, port->membase + LTQ_ASC_CON);
|
||||
|
||||
/* Set baud rate - take a divider of 2 into account */
|
||||
baud = uart_get_baud_rate(port, new, old, 0, port->uartclk / 16);
|
||||
divisor = uart_get_divisor(port, baud);
|
||||
divisor = divisor / 2 - 1;
|
||||
|
||||
/* disable the baudrate generator */
|
||||
ltq_w32_mask(ASCCON_R, 0, port->membase + LTQ_ASC_CON);
|
||||
|
||||
/* make sure the fractional divider is off */
|
||||
ltq_w32_mask(ASCCON_FDE, 0, port->membase + LTQ_ASC_CON);
|
||||
|
||||
/* set up to use divisor of 2 */
|
||||
ltq_w32_mask(ASCCON_BRS, 0, port->membase + LTQ_ASC_CON);
|
||||
|
||||
/* now we can write the new baudrate into the register */
|
||||
ltq_w32(divisor, port->membase + LTQ_ASC_BG);
|
||||
|
||||
/* turn the baudrate generator back on */
|
||||
ltq_w32_mask(0, ASCCON_R, port->membase + LTQ_ASC_CON);
|
||||
|
||||
/* enable rx */
|
||||
ltq_w32(ASCWHBSTATE_SETREN, port->membase + LTQ_ASC_WHBSTATE);
|
||||
|
||||
spin_unlock_irqrestore(<q_asc_lock, flags);
|
||||
|
||||
/* Don't rewrite B0 */
|
||||
if (tty_termios_baud_rate(new))
|
||||
tty_termios_encode_baud_rate(new, baud, baud);
|
||||
}
|
||||
|
||||
static const char*
|
||||
lqasc_type(struct uart_port *port)
|
||||
{
|
||||
if (port->type == PORT_LTQ_ASC)
|
||||
return DRVNAME;
|
||||
else
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static void
|
||||
lqasc_release_port(struct uart_port *port)
|
||||
{
|
||||
if (port->flags & UPF_IOREMAP) {
|
||||
iounmap(port->membase);
|
||||
port->membase = NULL;
|
||||
}
|
||||
}
|
||||
|
||||
static int
|
||||
lqasc_request_port(struct uart_port *port)
|
||||
{
|
||||
struct platform_device *pdev = to_platform_device(port->dev);
|
||||
struct resource *res;
|
||||
int size;
|
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
if (!res) {
|
||||
dev_err(&pdev->dev, "cannot obtain I/O memory region");
|
||||
return -ENODEV;
|
||||
}
|
||||
size = resource_size(res);
|
||||
|
||||
res = devm_request_mem_region(&pdev->dev, res->start,
|
||||
size, dev_name(&pdev->dev));
|
||||
if (!res) {
|
||||
dev_err(&pdev->dev, "cannot request I/O memory region");
|
||||
return -EBUSY;
|
||||
}
|
||||
|
||||
if (port->flags & UPF_IOREMAP) {
|
||||
port->membase = devm_ioremap_nocache(&pdev->dev,
|
||||
port->mapbase, size);
|
||||
if (port->membase == NULL)
|
||||
return -ENOMEM;
|
||||
}
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void
|
||||
lqasc_config_port(struct uart_port *port, int flags)
|
||||
{
|
||||
if (flags & UART_CONFIG_TYPE) {
|
||||
port->type = PORT_LTQ_ASC;
|
||||
lqasc_request_port(port);
|
||||
}
|
||||
}
|
||||
|
||||
static int
|
||||
lqasc_verify_port(struct uart_port *port,
|
||||
struct serial_struct *ser)
|
||||
{
|
||||
int ret = 0;
|
||||
if (ser->type != PORT_UNKNOWN && ser->type != PORT_LTQ_ASC)
|
||||
ret = -EINVAL;
|
||||
if (ser->irq < 0 || ser->irq >= NR_IRQS)
|
||||
ret = -EINVAL;
|
||||
if (ser->baud_base < 9600)
|
||||
ret = -EINVAL;
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct uart_ops lqasc_pops = {
|
||||
.tx_empty = lqasc_tx_empty,
|
||||
.set_mctrl = lqasc_set_mctrl,
|
||||
.get_mctrl = lqasc_get_mctrl,
|
||||
.stop_tx = lqasc_stop_tx,
|
||||
.start_tx = lqasc_start_tx,
|
||||
.stop_rx = lqasc_stop_rx,
|
||||
.enable_ms = lqasc_enable_ms,
|
||||
.break_ctl = lqasc_break_ctl,
|
||||
.startup = lqasc_startup,
|
||||
.shutdown = lqasc_shutdown,
|
||||
.set_termios = lqasc_set_termios,
|
||||
.type = lqasc_type,
|
||||
.release_port = lqasc_release_port,
|
||||
.request_port = lqasc_request_port,
|
||||
.config_port = lqasc_config_port,
|
||||
.verify_port = lqasc_verify_port,
|
||||
};
|
||||
|
||||
static void
|
||||
lqasc_console_putchar(struct uart_port *port, int ch)
|
||||
{
|
||||
int fifofree;
|
||||
|
||||
if (!port->membase)
|
||||
return;
|
||||
|
||||
do {
|
||||
fifofree = (ltq_r32(port->membase + LTQ_ASC_FSTAT)
|
||||
& ASCFSTAT_TXFREEMASK) >> ASCFSTAT_TXFREEOFF;
|
||||
} while (fifofree == 0);
|
||||
ltq_w8(ch, port->membase + LTQ_ASC_TBUF);
|
||||
}
|
||||
|
||||
|
||||
static void
|
||||
lqasc_console_write(struct console *co, const char *s, u_int count)
|
||||
{
|
||||
struct ltq_uart_port *ltq_port;
|
||||
struct uart_port *port;
|
||||
unsigned long flags;
|
||||
|
||||
if (co->index >= MAXPORTS)
|
||||
return;
|
||||
|
||||
ltq_port = lqasc_port[co->index];
|
||||
if (!ltq_port)
|
||||
return;
|
||||
|
||||
port = <q_port->port;
|
||||
|
||||
spin_lock_irqsave(<q_asc_lock, flags);
|
||||
uart_console_write(port, s, count, lqasc_console_putchar);
|
||||
spin_unlock_irqrestore(<q_asc_lock, flags);
|
||||
}
|
||||
|
||||
static int __init
|
||||
lqasc_console_setup(struct console *co, char *options)
|
||||
{
|
||||
struct ltq_uart_port *ltq_port;
|
||||
struct uart_port *port;
|
||||
int baud = 115200;
|
||||
int bits = 8;
|
||||
int parity = 'n';
|
||||
int flow = 'n';
|
||||
|
||||
if (co->index >= MAXPORTS)
|
||||
return -ENODEV;
|
||||
|
||||
ltq_port = lqasc_port[co->index];
|
||||
if (!ltq_port)
|
||||
return -ENODEV;
|
||||
|
||||
port = <q_port->port;
|
||||
|
||||
port->uartclk = clk_get_rate(ltq_port->clk);
|
||||
|
||||
if (options)
|
||||
uart_parse_options(options, &baud, &parity, &bits, &flow);
|
||||
return uart_set_options(port, co, baud, parity, bits, flow);
|
||||
}
|
||||
|
||||
static struct console lqasc_console = {
|
||||
.name = "ttyLTQ",
|
||||
.write = lqasc_console_write,
|
||||
.device = uart_console_device,
|
||||
.setup = lqasc_console_setup,
|
||||
.flags = CON_PRINTBUFFER,
|
||||
.index = -1,
|
||||
.data = &lqasc_reg,
|
||||
};
|
||||
|
||||
static int __init
|
||||
lqasc_console_init(void)
|
||||
{
|
||||
register_console(&lqasc_console);
|
||||
return 0;
|
||||
}
|
||||
console_initcall(lqasc_console_init);
|
||||
|
||||
static struct uart_driver lqasc_reg = {
|
||||
.owner = THIS_MODULE,
|
||||
.driver_name = DRVNAME,
|
||||
.dev_name = "ttyLTQ",
|
||||
.major = 0,
|
||||
.minor = 0,
|
||||
.nr = MAXPORTS,
|
||||
.cons = &lqasc_console,
|
||||
};
|
||||
|
||||
static int __init
|
||||
lqasc_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct ltq_uart_port *ltq_port;
|
||||
struct uart_port *port;
|
||||
struct resource *mmres, *irqres;
|
||||
int tx_irq, rx_irq, err_irq;
|
||||
struct clk *clk;
|
||||
int ret;
|
||||
|
||||
mmres = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
irqres = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
|
||||
if (!mmres || !irqres)
|
||||
return -ENODEV;
|
||||
|
||||
if (pdev->id >= MAXPORTS)
|
||||
return -EBUSY;
|
||||
|
||||
if (lqasc_port[pdev->id] != NULL)
|
||||
return -EBUSY;
|
||||
|
||||
clk = clk_get(&pdev->dev, "fpi");
|
||||
if (IS_ERR(clk)) {
|
||||
pr_err("failed to get fpi clk\n");
|
||||
return -ENOENT;
|
||||
}
|
||||
|
||||
tx_irq = platform_get_irq_byname(pdev, "tx");
|
||||
rx_irq = platform_get_irq_byname(pdev, "rx");
|
||||
err_irq = platform_get_irq_byname(pdev, "err");
|
||||
if ((tx_irq < 0) | (rx_irq < 0) | (err_irq < 0))
|
||||
return -ENODEV;
|
||||
|
||||
ltq_port = kzalloc(sizeof(struct ltq_uart_port), GFP_KERNEL);
|
||||
if (!ltq_port)
|
||||
return -ENOMEM;
|
||||
|
||||
port = <q_port->port;
|
||||
|
||||
port->iotype = SERIAL_IO_MEM;
|
||||
port->flags = ASYNC_BOOT_AUTOCONF | UPF_IOREMAP;
|
||||
port->ops = &lqasc_pops;
|
||||
port->fifosize = 16;
|
||||
port->type = PORT_LTQ_ASC,
|
||||
port->line = pdev->id;
|
||||
port->dev = &pdev->dev;
|
||||
|
||||
port->irq = tx_irq; /* unused, just to be backward-compatibe */
|
||||
port->mapbase = mmres->start;
|
||||
|
||||
ltq_port->clk = clk;
|
||||
|
||||
ltq_port->tx_irq = tx_irq;
|
||||
ltq_port->rx_irq = rx_irq;
|
||||
ltq_port->err_irq = err_irq;
|
||||
|
||||
lqasc_port[pdev->id] = ltq_port;
|
||||
platform_set_drvdata(pdev, ltq_port);
|
||||
|
||||
ret = uart_add_one_port(&lqasc_reg, port);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct platform_driver lqasc_driver = {
|
||||
.driver = {
|
||||
.name = DRVNAME,
|
||||
.owner = THIS_MODULE,
|
||||
},
|
||||
};
|
||||
|
||||
int __init
|
||||
init_lqasc(void)
|
||||
{
|
||||
int ret;
|
||||
|
||||
ret = uart_register_driver(&lqasc_reg);
|
||||
if (ret != 0)
|
||||
return ret;
|
||||
|
||||
ret = platform_driver_probe(&lqasc_driver, lqasc_probe);
|
||||
if (ret != 0)
|
||||
uart_unregister_driver(&lqasc_reg);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
module_init(init_lqasc);
|
||||
|
||||
MODULE_DESCRIPTION("Lantiq serial port driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
Loading…
Reference in New Issue
Block a user