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MIPS: Alchemy: sleepcode without compile-time cputype dependencies
Split the low-level sleepcode into per-cpu functions instead of relying on compile-time-defined cpu type. Signed-off-by: Manuel Lauss <manuel.lauss@gmail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: http://patchwork.linux-mips.org/patch/1281/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -193,9 +193,15 @@ static void restore_core_regs(void)
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void au_sleep(void)
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{
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save_core_regs();
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au1xxx_save_and_sleep();
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restore_core_regs();
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int cpuid = alchemy_get_cputype();
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if (cpuid != ALCHEMY_CPU_UNKNOWN) {
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save_core_regs();
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if (cpuid <= ALCHEMY_CPU_AU1500)
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alchemy_sleep_au1000();
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else if (cpuid <= ALCHEMY_CPU_AU1200)
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alchemy_sleep_au1550();
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restore_core_regs();
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}
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}
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#endif /* CONFIG_PM */
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@ -22,10 +22,9 @@
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.set noat
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.align 5
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/* Save all of the processor general registers and go to sleep.
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* A wakeup condition will get us back here to restore the registers.
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*/
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LEAF(au1xxx_save_and_sleep)
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/* preparatory stuff */
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.macro SETUP_SLEEP
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subu sp, PT_SIZE
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sw $1, PT_R1(sp)
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sw $2, PT_R2(sp)
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@ -69,12 +68,32 @@ LEAF(au1xxx_save_and_sleep)
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*/
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lui t3, 0xb190 /* sys_xxx */
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sw sp, 0x0018(t3)
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la k0, 3f /* resume path */
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la k0, alchemy_sleep_wakeup /* resume path */
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sw k0, 0x001c(t3)
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.endm
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/* Put SDRAM into self refresh: Preload instructions into cache,
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* issue a precharge, auto/self refresh, then sleep commands to it.
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*/
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.macro DO_SLEEP
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/* put power supply and processor to sleep */
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sw zero, 0x0078(t3) /* sys_slppwr */
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sync
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sw zero, 0x007c(t3) /* sys_sleep */
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sync
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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.endm
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/* sleep code for Au1000/Au1100/Au1500 memory controller type */
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LEAF(alchemy_sleep_au1000)
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SETUP_SLEEP
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/* cache following instructions, as memory gets put to sleep */
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la t0, 1f
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.set mips3
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cache 0x14, 0(t0)
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@ -84,17 +103,32 @@ LEAF(au1xxx_save_and_sleep)
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.set mips0
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1: lui a0, 0xb400 /* mem_xxx */
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#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1100) || \
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defined(CONFIG_SOC_AU1500)
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sw zero, 0x001c(a0) /* Precharge */
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sync
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sw zero, 0x0020(a0) /* Auto Refresh */
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sync
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sw zero, 0x0030(a0) /* Sleep */
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sync
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#endif
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#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
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DO_SLEEP
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END(alchemy_sleep_au1000)
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/* sleep code for Au1550/Au1200 memory controller type */
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LEAF(alchemy_sleep_au1550)
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SETUP_SLEEP
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/* cache following instructions, as memory gets put to sleep */
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la t0, 1f
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.set mips3
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cache 0x14, 0(t0)
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cache 0x14, 32(t0)
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cache 0x14, 64(t0)
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cache 0x14, 96(t0)
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.set mips0
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1: lui a0, 0xb400 /* mem_xxx */
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sw zero, 0x08c0(a0) /* Precharge */
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sync
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sw zero, 0x08d0(a0) /* Self Refresh */
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@ -114,26 +148,17 @@ LEAF(au1xxx_save_and_sleep)
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and t1, t0, t1 /* clear CE[1:0] */
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sw t1, 0x0840(a0) /* mem_sdconfiga */
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sync
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#endif
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/* put power supply and processor to sleep */
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sw zero, 0x0078(t3) /* sys_slppwr */
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sync
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sw zero, 0x007c(t3) /* sys_sleep */
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sync
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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nop
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DO_SLEEP
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END(alchemy_sleep_au1550)
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/* This is where we return upon wakeup.
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* Reload all of the registers and return.
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*/
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3: lw k0, 0x20(sp)
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LEAF(alchemy_sleep_wakeup)
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lw k0, 0x20(sp)
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mtc0 k0, CP0_STATUS
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lw k0, 0x1c(sp)
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mtc0 k0, CP0_CONTEXT
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@ -169,4 +194,4 @@ LEAF(au1xxx_save_and_sleep)
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lw $31, PT_R31(sp)
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jr ra
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addiu sp, PT_SIZE
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END(au1xxx_save_and_sleep)
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END(alchemy_sleep_wakeup)
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@ -188,7 +188,8 @@ extern unsigned long get_au1x00_uart_baud_base(void);
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extern unsigned long au1xxx_calc_clock(void);
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/* PM: arch/mips/alchemy/common/sleeper.S, power.c, irq.c */
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void au1xxx_save_and_sleep(void);
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void alchemy_sleep_au1000(void);
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void alchemy_sleep_au1550(void);
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void au_sleep(void);
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