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Merge branch 'v4.16-fixes'
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commit
2e8ebed6ed
@ -232,11 +232,14 @@ static int aspeed_wdt_probe(struct platform_device *pdev)
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wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC | WDT_CTRL_RESET_SYSTEM;
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} else {
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if (!strcmp(reset_type, "cpu"))
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wdt->ctrl |= WDT_CTRL_RESET_MODE_ARM_CPU;
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wdt->ctrl |= WDT_CTRL_RESET_MODE_ARM_CPU |
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WDT_CTRL_RESET_SYSTEM;
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else if (!strcmp(reset_type, "soc"))
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wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC;
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wdt->ctrl |= WDT_CTRL_RESET_MODE_SOC |
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WDT_CTRL_RESET_SYSTEM;
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else if (!strcmp(reset_type, "system"))
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wdt->ctrl |= WDT_CTRL_RESET_SYSTEM;
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wdt->ctrl |= WDT_CTRL_RESET_MODE_FULL_CHIP |
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WDT_CTRL_RESET_SYSTEM;
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else if (strcmp(reset_type, "none"))
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return -EINVAL;
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}
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@ -34,6 +34,7 @@
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#define WDOG_CONTROL_REG_OFFSET 0x00
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#define WDOG_CONTROL_REG_WDT_EN_MASK 0x01
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#define WDOG_CONTROL_REG_RESP_MODE_MASK 0x02
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#define WDOG_TIMEOUT_RANGE_REG_OFFSET 0x04
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#define WDOG_TIMEOUT_RANGE_TOPINIT_SHIFT 4
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#define WDOG_CURRENT_COUNT_REG_OFFSET 0x08
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@ -56,6 +57,9 @@ struct dw_wdt {
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unsigned long rate;
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struct watchdog_device wdd;
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struct reset_control *rst;
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/* Save/restore */
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u32 control;
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u32 timeout;
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};
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#define to_dw_wdt(wdd) container_of(wdd, struct dw_wdt, wdd)
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@ -121,14 +125,23 @@ static int dw_wdt_set_timeout(struct watchdog_device *wdd, unsigned int top_s)
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return 0;
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}
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static void dw_wdt_arm_system_reset(struct dw_wdt *dw_wdt)
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{
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u32 val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
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/* Disable interrupt mode; always perform system reset. */
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val &= ~WDOG_CONTROL_REG_RESP_MODE_MASK;
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/* Enable watchdog. */
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val |= WDOG_CONTROL_REG_WDT_EN_MASK;
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writel(val, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
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}
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static int dw_wdt_start(struct watchdog_device *wdd)
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{
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struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
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dw_wdt_set_timeout(wdd, wdd->timeout);
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writel(WDOG_CONTROL_REG_WDT_EN_MASK,
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dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
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dw_wdt_arm_system_reset(dw_wdt);
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return 0;
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}
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@ -152,16 +165,13 @@ static int dw_wdt_restart(struct watchdog_device *wdd,
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unsigned long action, void *data)
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{
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struct dw_wdt *dw_wdt = to_dw_wdt(wdd);
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u32 val;
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writel(0, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
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val = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
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if (val & WDOG_CONTROL_REG_WDT_EN_MASK)
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if (dw_wdt_is_enabled(dw_wdt))
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writel(WDOG_COUNTER_RESTART_KICK_VALUE,
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dw_wdt->regs + WDOG_COUNTER_RESTART_REG_OFFSET);
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else
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writel(WDOG_CONTROL_REG_WDT_EN_MASK,
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dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
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dw_wdt_arm_system_reset(dw_wdt);
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/* wait for reset to assert... */
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mdelay(500);
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@ -198,6 +208,9 @@ static int dw_wdt_suspend(struct device *dev)
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{
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struct dw_wdt *dw_wdt = dev_get_drvdata(dev);
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dw_wdt->control = readl(dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
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dw_wdt->timeout = readl(dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
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clk_disable_unprepare(dw_wdt->clk);
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return 0;
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@ -211,6 +224,9 @@ static int dw_wdt_resume(struct device *dev)
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if (err)
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return err;
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writel(dw_wdt->timeout, dw_wdt->regs + WDOG_TIMEOUT_RANGE_REG_OFFSET);
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writel(dw_wdt->control, dw_wdt->regs + WDOG_CONTROL_REG_OFFSET);
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dw_wdt_ping(&dw_wdt->wdd);
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return 0;
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@ -154,8 +154,10 @@ static int sprd_wdt_enable(struct sprd_wdt *wdt)
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if (ret)
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return ret;
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ret = clk_prepare_enable(wdt->rtc_enable);
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if (ret)
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if (ret) {
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clk_disable_unprepare(wdt->enable);
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return ret;
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}
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sprd_wdt_unlock(wdt->base);
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val = readl_relaxed(wdt->base + SPRD_WDT_CTRL);
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