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drm fixes for 6.10-rc3
xe: - Update the LMTT when freeing VF GT config amdgpu: - Fix shutdown issues on some SMU 13.x platforms - Silence some UBSAN flexible array warnings panel: - sitronix-st7789v: handle of_drm_get_panel_orientation failing error. vmwgfx: - filter modes greater than available graphics memory - fix 3D vs STDU enable - remove STDU logic from mode valid - logging fix - memcmp pointers fix - remove unused struct - screen target lifetime fix komeda: - unused struct removal -----BEGIN PGP SIGNATURE----- iQIzBAABCAAdFiEEEKbZHaGwW9KfbeusDHTzWXnEhr4FAmZiaO8ACgkQDHTzWXnE hr4yhA/+LgXtif5TqGp2q//ILQ25xKRZ59bZTc0UUvjX+egNOk/Sp81U9ISBsNO2 OGNmyCZ7PGC6NfsYTBHDrtXbTyqGsW+xVGH7YXe3fpSy99pNwjCSmAcdVeqycbY6 X3dPezUoNEbWemno6HUaBpVQQlo/j7SxBchyPVmzfy9zLzp8g2nt3LKrJPciBjCm uxqDf+vQLeh7O0jUcEMsFHEHOlq7o6/IZZebrhhph62AyLKtWztJt5CU2C5wobMh 5eNEc/Sp8ErwdBUZL6DaxM0TiAi2WLI2T6/fNozK358UyGe8En6cT8I87sphRprc ylMgfzRagqRqi8zV1Ctfr2VeyyjS6xeXYTVVEPmpjqOv6QZOsIIx2D67qffzT1bx 2tfRo4Ix0is7ryk3BdEv7K6tTErswqOf72YAg94lLB/4AVDrv+rUOsMjNnSKpz0F Dm7MVz7HUi/soKC7tZh5rTtJHLRWFOnIVwpe07crTFpITGdj6PGg/KxtRqwMOkjO DT0zXfblzlnCJM23WQmV5YppXP/38vUTSZrchTZF4aEd378fnyb4L/7TLKuZ84R2 mjtVMO9nGEiwIS1fTVLUg1ySXpm9FsWeMummxjGNXmhh2OBj4D3LTESulTnVLhL6 43o2a2o3oNS3nUoZqncd4j35NkjmqjwG//Ss5+ps7iMSu69abX8= =iAM2 -----END PGP SIGNATURE----- Merge tag 'drm-fixes-2024-06-07' of https://gitlab.freedesktop.org/drm/kernel Pull drm fixes from Dave Airlie: "Weekly fixes: vmwgfx leads the way this week, with minor changes in xe and amdgpu and a couple of other small fixes. Seems quiet enough. xe: - Update the LMTT when freeing VF GT config amdgpu: - Fix shutdown issues on some SMU 13.x platforms - Silence some UBSAN flexible array warnings panel: - sitronix-st7789v: handle of_drm_get_panel_orientation failing error vmwgfx: - filter modes greater than available graphics memory - fix 3D vs STDU enable - remove STDU logic from mode valid - logging fix - memcmp pointers fix - remove unused struct - screen target lifetime fix komeda: - unused struct removal" * tag 'drm-fixes-2024-06-07' of https://gitlab.freedesktop.org/drm/kernel: drm/vmwgfx: Don't memcmp equivalent pointers drm/vmwgfx: remove unused struct 'vmw_stdu_dma' drm/vmwgfx: Don't destroy Screen Target when CRTC is enabled but inactive drm/vmwgfx: Standardize use of kibibytes when logging drm/vmwgfx: Remove STDU logic from generic mode_valid function drm/vmwgfx: 3D disabled should not effect STDU memory limits drm/vmwgfx: Filter modes which exceed graphics memory drm/amdgpu/pptable: Fix UBSAN array-index-out-of-bounds drm/amd: Fix shutdown (again) on some SMU v13.0.4/11 platforms drm/xe/pf: Update the LMTT when freeing VF GT config drm/panel: sitronix-st7789v: Add check for of_drm_get_panel_orientation drm/komeda: remove unused struct 'gamma_curve_segment'
This commit is contained in:
commit
2e32d58075
@ -477,31 +477,30 @@ typedef struct _ATOM_PPLIB_STATE_V2
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} ATOM_PPLIB_STATE_V2;
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typedef struct _StateArray{
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//how many states we have
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UCHAR ucNumEntries;
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ATOM_PPLIB_STATE_V2 states[1];
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//how many states we have
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UCHAR ucNumEntries;
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ATOM_PPLIB_STATE_V2 states[] /* __counted_by(ucNumEntries) */;
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}StateArray;
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typedef struct _ClockInfoArray{
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//how many clock levels we have
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UCHAR ucNumEntries;
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//sizeof(ATOM_PPLIB_CLOCK_INFO)
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UCHAR ucEntrySize;
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UCHAR clockInfo[];
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//how many clock levels we have
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UCHAR ucNumEntries;
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//sizeof(ATOM_PPLIB_CLOCK_INFO)
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UCHAR ucEntrySize;
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UCHAR clockInfo[];
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}ClockInfoArray;
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typedef struct _NonClockInfoArray{
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//how many non-clock levels we have. normally should be same as number of states
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UCHAR ucNumEntries;
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//sizeof(ATOM_PPLIB_NONCLOCK_INFO)
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UCHAR ucEntrySize;
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//how many non-clock levels we have. normally should be same as number of states
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UCHAR ucNumEntries;
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//sizeof(ATOM_PPLIB_NONCLOCK_INFO)
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UCHAR ucEntrySize;
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ATOM_PPLIB_NONCLOCK_INFO nonClockInfo[];
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ATOM_PPLIB_NONCLOCK_INFO nonClockInfo[] __counted_by(ucNumEntries);
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}NonClockInfoArray;
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typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Record
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@ -513,8 +512,10 @@ typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Record
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typedef struct _ATOM_PPLIB_Clock_Voltage_Dependency_Table
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{
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UCHAR ucNumEntries; // Number of entries.
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ATOM_PPLIB_Clock_Voltage_Dependency_Record entries[1]; // Dynamically allocate entries.
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// Number of entries.
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UCHAR ucNumEntries;
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// Dynamically allocate entries.
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ATOM_PPLIB_Clock_Voltage_Dependency_Record entries[] __counted_by(ucNumEntries);
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}ATOM_PPLIB_Clock_Voltage_Dependency_Table;
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typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Record
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@ -529,8 +530,10 @@ typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Record
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typedef struct _ATOM_PPLIB_Clock_Voltage_Limit_Table
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{
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UCHAR ucNumEntries; // Number of entries.
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ATOM_PPLIB_Clock_Voltage_Limit_Record entries[1]; // Dynamically allocate entries.
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// Number of entries.
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UCHAR ucNumEntries;
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// Dynamically allocate entries.
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ATOM_PPLIB_Clock_Voltage_Limit_Record entries[] __counted_by(ucNumEntries);
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}ATOM_PPLIB_Clock_Voltage_Limit_Table;
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union _ATOM_PPLIB_CAC_Leakage_Record
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@ -553,8 +556,10 @@ typedef union _ATOM_PPLIB_CAC_Leakage_Record ATOM_PPLIB_CAC_Leakage_Record;
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typedef struct _ATOM_PPLIB_CAC_Leakage_Table
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{
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UCHAR ucNumEntries; // Number of entries.
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ATOM_PPLIB_CAC_Leakage_Record entries[1]; // Dynamically allocate entries.
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// Number of entries.
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UCHAR ucNumEntries;
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// Dynamically allocate entries.
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ATOM_PPLIB_CAC_Leakage_Record entries[] __counted_by(ucNumEntries);
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}ATOM_PPLIB_CAC_Leakage_Table;
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typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Record
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@ -568,8 +573,10 @@ typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Record
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typedef struct _ATOM_PPLIB_PhaseSheddingLimits_Table
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{
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UCHAR ucNumEntries; // Number of entries.
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ATOM_PPLIB_PhaseSheddingLimits_Record entries[1]; // Dynamically allocate entries.
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// Number of entries.
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UCHAR ucNumEntries;
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// Dynamically allocate entries.
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ATOM_PPLIB_PhaseSheddingLimits_Record entries[] __counted_by(ucNumEntries);
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}ATOM_PPLIB_PhaseSheddingLimits_Table;
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typedef struct _VCEClockInfo{
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@ -580,8 +587,8 @@ typedef struct _VCEClockInfo{
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}VCEClockInfo;
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typedef struct _VCEClockInfoArray{
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UCHAR ucNumEntries;
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VCEClockInfo entries[1];
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UCHAR ucNumEntries;
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VCEClockInfo entries[] __counted_by(ucNumEntries);
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}VCEClockInfoArray;
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typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record
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@ -592,8 +599,8 @@ typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record
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typedef struct _ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table
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{
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UCHAR numEntries;
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ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record entries[1];
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UCHAR numEntries;
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ATOM_PPLIB_VCE_Clock_Voltage_Limit_Record entries[] __counted_by(numEntries);
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}ATOM_PPLIB_VCE_Clock_Voltage_Limit_Table;
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typedef struct _ATOM_PPLIB_VCE_State_Record
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@ -604,8 +611,8 @@ typedef struct _ATOM_PPLIB_VCE_State_Record
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typedef struct _ATOM_PPLIB_VCE_State_Table
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{
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UCHAR numEntries;
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ATOM_PPLIB_VCE_State_Record entries[1];
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UCHAR numEntries;
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ATOM_PPLIB_VCE_State_Record entries[] __counted_by(numEntries);
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}ATOM_PPLIB_VCE_State_Table;
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@ -626,8 +633,8 @@ typedef struct _UVDClockInfo{
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}UVDClockInfo;
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typedef struct _UVDClockInfoArray{
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UCHAR ucNumEntries;
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UVDClockInfo entries[1];
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UCHAR ucNumEntries;
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UVDClockInfo entries[] __counted_by(ucNumEntries);
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}UVDClockInfoArray;
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typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record
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@ -638,8 +645,8 @@ typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record
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typedef struct _ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table
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{
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UCHAR numEntries;
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ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record entries[1];
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UCHAR numEntries;
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ATOM_PPLIB_UVD_Clock_Voltage_Limit_Record entries[] __counted_by(numEntries);
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}ATOM_PPLIB_UVD_Clock_Voltage_Limit_Table;
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typedef struct _ATOM_PPLIB_UVD_Table
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@ -657,8 +664,8 @@ typedef struct _ATOM_PPLIB_SAMClk_Voltage_Limit_Record
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}ATOM_PPLIB_SAMClk_Voltage_Limit_Record;
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typedef struct _ATOM_PPLIB_SAMClk_Voltage_Limit_Table{
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UCHAR numEntries;
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ATOM_PPLIB_SAMClk_Voltage_Limit_Record entries[];
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UCHAR numEntries;
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ATOM_PPLIB_SAMClk_Voltage_Limit_Record entries[] __counted_by(numEntries);
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}ATOM_PPLIB_SAMClk_Voltage_Limit_Table;
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typedef struct _ATOM_PPLIB_SAMU_Table
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@ -675,8 +682,8 @@ typedef struct _ATOM_PPLIB_ACPClk_Voltage_Limit_Record
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}ATOM_PPLIB_ACPClk_Voltage_Limit_Record;
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typedef struct _ATOM_PPLIB_ACPClk_Voltage_Limit_Table{
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UCHAR numEntries;
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ATOM_PPLIB_ACPClk_Voltage_Limit_Record entries[1];
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UCHAR numEntries;
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ATOM_PPLIB_ACPClk_Voltage_Limit_Record entries[] __counted_by(numEntries);
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}ATOM_PPLIB_ACPClk_Voltage_Limit_Table;
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typedef struct _ATOM_PPLIB_ACP_Table
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@ -743,9 +750,9 @@ typedef struct ATOM_PPLIB_VQ_Budgeting_Record{
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} ATOM_PPLIB_VQ_Budgeting_Record;
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typedef struct ATOM_PPLIB_VQ_Budgeting_Table {
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UCHAR revid;
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UCHAR numEntries;
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ATOM_PPLIB_VQ_Budgeting_Record entries[1];
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UCHAR revid;
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UCHAR numEntries;
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ATOM_PPLIB_VQ_Budgeting_Record entries[] __counted_by(numEntries);
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} ATOM_PPLIB_VQ_Budgeting_Table;
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#pragma pack()
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@ -226,15 +226,17 @@ static int smu_v13_0_4_system_features_control(struct smu_context *smu, bool en)
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struct amdgpu_device *adev = smu->adev;
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int ret = 0;
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if (!en && adev->in_s4) {
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/* Adds a GFX reset as workaround just before sending the
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* MP1_UNLOAD message to prevent GC/RLC/PMFW from entering
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* an invalid state.
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*/
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ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset,
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SMU_RESET_MODE_2, NULL);
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if (ret)
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return ret;
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if (!en && !adev->in_s0ix) {
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if (adev->in_s4) {
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/* Adds a GFX reset as workaround just before sending the
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* MP1_UNLOAD message to prevent GC/RLC/PMFW from entering
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* an invalid state.
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*/
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ret = smu_cmn_send_smc_msg_with_param(smu, SMU_MSG_GfxDeviceDriverReset,
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SMU_RESET_MODE_2, NULL);
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if (ret)
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return ret;
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}
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ret = smu_cmn_send_smc_msg(smu, SMU_MSG_PrepareMp1ForUnload, NULL);
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}
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@ -72,11 +72,6 @@ struct gamma_curve_sector {
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u32 segment_width;
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};
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struct gamma_curve_segment {
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u32 start;
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u32 end;
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};
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static struct gamma_curve_sector sector_tbl[] = {
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{ 0, 4, 4 },
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{ 16, 4, 4 },
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@ -643,7 +643,9 @@ static int st7789v_probe(struct spi_device *spi)
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if (ret)
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return dev_err_probe(dev, ret, "Failed to get backlight\n");
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of_drm_get_panel_orientation(spi->dev.of_node, &ctx->orientation);
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ret = of_drm_get_panel_orientation(spi->dev.of_node, &ctx->orientation);
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if (ret)
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return dev_err_probe(&spi->dev, ret, "Failed to get orientation\n");
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drm_panel_add(&ctx->panel);
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@ -746,7 +746,7 @@ static int vmw_setup_pci_resources(struct vmw_private *dev,
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dev->vram_size = pci_resource_len(pdev, 2);
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drm_info(&dev->drm,
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"Register MMIO at 0x%pa size is %llu kiB\n",
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"Register MMIO at 0x%pa size is %llu KiB\n",
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&rmmio_start, (uint64_t)rmmio_size / 1024);
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dev->rmmio = devm_ioremap(dev->drm.dev,
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rmmio_start,
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@ -765,7 +765,7 @@ static int vmw_setup_pci_resources(struct vmw_private *dev,
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fifo_size = pci_resource_len(pdev, 2);
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drm_info(&dev->drm,
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"FIFO at %pa size is %llu kiB\n",
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"FIFO at %pa size is %llu KiB\n",
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&fifo_start, (uint64_t)fifo_size / 1024);
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dev->fifo_mem = devm_memremap(dev->drm.dev,
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fifo_start,
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@ -790,7 +790,7 @@ static int vmw_setup_pci_resources(struct vmw_private *dev,
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* SVGA_REG_VRAM_SIZE.
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*/
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drm_info(&dev->drm,
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"VRAM at %pa size is %llu kiB\n",
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"VRAM at %pa size is %llu KiB\n",
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&dev->vram_start, (uint64_t)dev->vram_size / 1024);
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return 0;
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@ -960,13 +960,6 @@ static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id)
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vmw_read(dev_priv,
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SVGA_REG_SUGGESTED_GBOBJECT_MEM_SIZE_KB);
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/*
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* Workaround for low memory 2D VMs to compensate for the
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* allocation taken by fbdev
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*/
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if (!(dev_priv->capabilities & SVGA_CAP_3D))
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mem_size *= 3;
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dev_priv->max_mob_pages = mem_size * 1024 / PAGE_SIZE;
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dev_priv->max_primary_mem =
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vmw_read(dev_priv, SVGA_REG_MAX_PRIMARY_MEM);
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@ -991,13 +984,13 @@ static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id)
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dev_priv->max_primary_mem = dev_priv->vram_size;
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}
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drm_info(&dev_priv->drm,
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"Legacy memory limits: VRAM = %llu kB, FIFO = %llu kB, surface = %u kB\n",
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"Legacy memory limits: VRAM = %llu KiB, FIFO = %llu KiB, surface = %u KiB\n",
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(u64)dev_priv->vram_size / 1024,
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(u64)dev_priv->fifo_mem_size / 1024,
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dev_priv->memory_size / 1024);
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drm_info(&dev_priv->drm,
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"MOB limits: max mob size = %u kB, max mob pages = %u\n",
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"MOB limits: max mob size = %u KiB, max mob pages = %u\n",
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dev_priv->max_mob_size / 1024, dev_priv->max_mob_pages);
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ret = vmw_dma_masks(dev_priv);
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@ -1015,7 +1008,7 @@ static int vmw_driver_load(struct vmw_private *dev_priv, u32 pci_id)
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(unsigned)dev_priv->max_gmr_pages);
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}
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drm_info(&dev_priv->drm,
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"Maximum display memory size is %llu kiB\n",
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"Maximum display memory size is %llu KiB\n",
|
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(uint64_t)dev_priv->max_primary_mem / 1024);
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|
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/* Need mmio memory to check for fifo pitchlock cap. */
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|
@ -1043,9 +1043,6 @@ void vmw_kms_cursor_snoop(struct vmw_surface *srf,
|
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int vmw_kms_write_svga(struct vmw_private *vmw_priv,
|
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unsigned width, unsigned height, unsigned pitch,
|
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unsigned bpp, unsigned depth);
|
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bool vmw_kms_validate_mode_vram(struct vmw_private *dev_priv,
|
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uint32_t pitch,
|
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uint32_t height);
|
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int vmw_kms_present(struct vmw_private *dev_priv,
|
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struct drm_file *file_priv,
|
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struct vmw_framebuffer *vfb,
|
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|
@ -94,14 +94,14 @@ static int vmw_gmrid_man_get_node(struct ttm_resource_manager *man,
|
||||
} else
|
||||
new_max_pages = gman->max_gmr_pages * 2;
|
||||
if (new_max_pages > gman->max_gmr_pages && new_max_pages >= gman->used_gmr_pages) {
|
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DRM_WARN("vmwgfx: increasing guest mob limits to %u kB.\n",
|
||||
DRM_WARN("vmwgfx: increasing guest mob limits to %u KiB.\n",
|
||||
((new_max_pages) << (PAGE_SHIFT - 10)));
|
||||
|
||||
gman->max_gmr_pages = new_max_pages;
|
||||
} else {
|
||||
char buf[256];
|
||||
snprintf(buf, sizeof(buf),
|
||||
"vmwgfx, error: guest graphics is out of memory (mob limit at: %ukB).\n",
|
||||
"vmwgfx, error: guest graphics is out of memory (mob limit at: %u KiB).\n",
|
||||
((gman->max_gmr_pages) << (PAGE_SHIFT - 10)));
|
||||
vmw_host_printf(buf);
|
||||
DRM_WARN("%s", buf);
|
||||
|
@ -224,7 +224,7 @@ static bool vmw_du_cursor_plane_has_changed(struct vmw_plane_state *old_vps,
|
||||
new_image = vmw_du_cursor_plane_acquire_image(new_vps);
|
||||
|
||||
changed = false;
|
||||
if (old_image && new_image)
|
||||
if (old_image && new_image && old_image != new_image)
|
||||
changed = memcmp(old_image, new_image, size) != 0;
|
||||
|
||||
return changed;
|
||||
@ -2171,13 +2171,12 @@ int vmw_kms_write_svga(struct vmw_private *vmw_priv,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static
|
||||
bool vmw_kms_validate_mode_vram(struct vmw_private *dev_priv,
|
||||
uint32_t pitch,
|
||||
uint32_t height)
|
||||
u64 pitch,
|
||||
u64 height)
|
||||
{
|
||||
return ((u64) pitch * (u64) height) < (u64)
|
||||
((dev_priv->active_display_unit == vmw_du_screen_target) ?
|
||||
dev_priv->max_primary_mem : dev_priv->vram_size);
|
||||
return (pitch * height) < (u64)dev_priv->vram_size;
|
||||
}
|
||||
|
||||
/**
|
||||
@ -2873,25 +2872,18 @@ out_unref:
|
||||
enum drm_mode_status vmw_connector_mode_valid(struct drm_connector *connector,
|
||||
struct drm_display_mode *mode)
|
||||
{
|
||||
enum drm_mode_status ret;
|
||||
struct drm_device *dev = connector->dev;
|
||||
struct vmw_private *dev_priv = vmw_priv(dev);
|
||||
u32 max_width = dev_priv->texture_max_width;
|
||||
u32 max_height = dev_priv->texture_max_height;
|
||||
u32 assumed_cpp = 4;
|
||||
|
||||
if (dev_priv->assume_16bpp)
|
||||
assumed_cpp = 2;
|
||||
|
||||
if (dev_priv->active_display_unit == vmw_du_screen_target) {
|
||||
max_width = min(dev_priv->stdu_max_width, max_width);
|
||||
max_height = min(dev_priv->stdu_max_height, max_height);
|
||||
}
|
||||
|
||||
if (max_width < mode->hdisplay)
|
||||
return MODE_BAD_HVALUE;
|
||||
|
||||
if (max_height < mode->vdisplay)
|
||||
return MODE_BAD_VVALUE;
|
||||
ret = drm_mode_validate_size(mode, dev_priv->texture_max_width,
|
||||
dev_priv->texture_max_height);
|
||||
if (ret != MODE_OK)
|
||||
return ret;
|
||||
|
||||
if (!vmw_kms_validate_mode_vram(dev_priv,
|
||||
mode->hdisplay * assumed_cpp,
|
||||
|
@ -43,7 +43,14 @@
|
||||
#define vmw_connector_to_stdu(x) \
|
||||
container_of(x, struct vmw_screen_target_display_unit, base.connector)
|
||||
|
||||
|
||||
/*
|
||||
* Some renderers such as llvmpipe will align the width and height of their
|
||||
* buffers to match their tile size. We need to keep this in mind when exposing
|
||||
* modes to userspace so that this possible over-allocation will not exceed
|
||||
* graphics memory. 64x64 pixels seems to be a reasonable upper bound for the
|
||||
* tile size of current renderers.
|
||||
*/
|
||||
#define GPU_TILE_SIZE 64
|
||||
|
||||
enum stdu_content_type {
|
||||
SAME_AS_DISPLAY = 0,
|
||||
@ -85,11 +92,6 @@ struct vmw_stdu_update {
|
||||
SVGA3dCmdUpdateGBScreenTarget body;
|
||||
};
|
||||
|
||||
struct vmw_stdu_dma {
|
||||
SVGA3dCmdHeader header;
|
||||
SVGA3dCmdSurfaceDMA body;
|
||||
};
|
||||
|
||||
struct vmw_stdu_surface_copy {
|
||||
SVGA3dCmdHeader header;
|
||||
SVGA3dCmdSurfaceCopy body;
|
||||
@ -414,6 +416,7 @@ static void vmw_stdu_crtc_atomic_disable(struct drm_crtc *crtc,
|
||||
{
|
||||
struct vmw_private *dev_priv;
|
||||
struct vmw_screen_target_display_unit *stdu;
|
||||
struct drm_crtc_state *new_crtc_state;
|
||||
int ret;
|
||||
|
||||
if (!crtc) {
|
||||
@ -423,6 +426,7 @@ static void vmw_stdu_crtc_atomic_disable(struct drm_crtc *crtc,
|
||||
|
||||
stdu = vmw_crtc_to_stdu(crtc);
|
||||
dev_priv = vmw_priv(crtc->dev);
|
||||
new_crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
|
||||
|
||||
if (dev_priv->vkms_enabled)
|
||||
drm_crtc_vblank_off(crtc);
|
||||
@ -434,6 +438,14 @@ static void vmw_stdu_crtc_atomic_disable(struct drm_crtc *crtc,
|
||||
|
||||
(void) vmw_stdu_update_st(dev_priv, stdu);
|
||||
|
||||
/* Don't destroy the Screen Target if we are only setting the
|
||||
* display as inactive
|
||||
*/
|
||||
if (new_crtc_state->enable &&
|
||||
!new_crtc_state->active &&
|
||||
!new_crtc_state->mode_changed)
|
||||
return;
|
||||
|
||||
ret = vmw_stdu_destroy_st(dev_priv, stdu);
|
||||
if (ret)
|
||||
DRM_ERROR("Failed to destroy Screen Target\n");
|
||||
@ -829,7 +841,41 @@ static void vmw_stdu_connector_destroy(struct drm_connector *connector)
|
||||
vmw_stdu_destroy(vmw_connector_to_stdu(connector));
|
||||
}
|
||||
|
||||
static enum drm_mode_status
|
||||
vmw_stdu_connector_mode_valid(struct drm_connector *connector,
|
||||
struct drm_display_mode *mode)
|
||||
{
|
||||
enum drm_mode_status ret;
|
||||
struct drm_device *dev = connector->dev;
|
||||
struct vmw_private *dev_priv = vmw_priv(dev);
|
||||
u64 assumed_cpp = dev_priv->assume_16bpp ? 2 : 4;
|
||||
/* Align width and height to account for GPU tile over-alignment */
|
||||
u64 required_mem = ALIGN(mode->hdisplay, GPU_TILE_SIZE) *
|
||||
ALIGN(mode->vdisplay, GPU_TILE_SIZE) *
|
||||
assumed_cpp;
|
||||
required_mem = ALIGN(required_mem, PAGE_SIZE);
|
||||
|
||||
ret = drm_mode_validate_size(mode, dev_priv->stdu_max_width,
|
||||
dev_priv->stdu_max_height);
|
||||
if (ret != MODE_OK)
|
||||
return ret;
|
||||
|
||||
ret = drm_mode_validate_size(mode, dev_priv->texture_max_width,
|
||||
dev_priv->texture_max_height);
|
||||
if (ret != MODE_OK)
|
||||
return ret;
|
||||
|
||||
if (required_mem > dev_priv->max_primary_mem)
|
||||
return MODE_MEM;
|
||||
|
||||
if (required_mem > dev_priv->max_mob_pages * PAGE_SIZE)
|
||||
return MODE_MEM;
|
||||
|
||||
if (required_mem > dev_priv->max_mob_size)
|
||||
return MODE_MEM;
|
||||
|
||||
return MODE_OK;
|
||||
}
|
||||
|
||||
static const struct drm_connector_funcs vmw_stdu_connector_funcs = {
|
||||
.dpms = vmw_du_connector_dpms,
|
||||
@ -845,7 +891,7 @@ static const struct drm_connector_funcs vmw_stdu_connector_funcs = {
|
||||
static const struct
|
||||
drm_connector_helper_funcs vmw_stdu_connector_helper_funcs = {
|
||||
.get_modes = vmw_connector_get_modes,
|
||||
.mode_valid = vmw_connector_mode_valid
|
||||
.mode_valid = vmw_stdu_connector_mode_valid
|
||||
};
|
||||
|
||||
|
||||
|
@ -1749,6 +1749,7 @@ static void pf_release_vf_config(struct xe_gt *gt, unsigned int vfid)
|
||||
if (!xe_gt_is_media_type(gt)) {
|
||||
pf_release_vf_config_ggtt(gt, config);
|
||||
pf_release_vf_config_lmem(gt, config);
|
||||
pf_update_vf_lmtt(gt_to_xe(gt), vfid);
|
||||
}
|
||||
pf_release_config_ctxs(gt, config);
|
||||
pf_release_config_dbs(gt, config);
|
||||
|
Loading…
Reference in New Issue
Block a user