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ARM64: DT: Hisilicon ARM64 DT updates for 5.11

Browse Source 
- Cleanups of the hisilicon DTS to align with the dtschema. All of them do not
   have any functional effect except passing dtschema checks or dtc W=2 builds.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJfvQU/AAoJEAvIV27ZiWZc5fkQAItkZPQdFd6SVnozLvTdRYOr
 656kay//xs/qaV2+rX57PgHqs+aw9DtuXqoAIP8UZ6toCUkEsk70j2PDx+315FQ4
 naTm3fvGLMfyd0b0AjgY8nBZtEgfZEddHgL5dR0OEDShGRJls1MRI84SFYNPCzkq
 ZwUMWctbqmNXAA2JbYXR5PgvVnmCPTUW8qSmtY53OKwQT4UAHP5jZx4g9PmPEE/X
 vPrTnPWeJ7DFbNLi4QryxlmlqdjM8INLSGF0mL+AyfDJ4AOk6iyWPreMwrIX3scG
 P8xSCmAZAxorIrbB3BrPAwfUyDCpi5/vGhgiiF6PWORpkRRPpXEQm/ZhKxOtGgvN
 aIErLncBGymS9rQ+izXNmEBbndhZoZESWrDQrWjfKsM22YwZhLmvQFmXXo32TURn
 6nWhs8kPopJ/kc3130LfMgCATuxkRVacK71mJi3iCPjkxVPnAzAUTXV7mxygGi0e
 21YwLM2UhZTfhFaNq1Q6i1zwYDnuYcP19ayTFsho7LFh35MaO1R5zHB2nMvEWUv6
 JiWvdZIYkve0GvKr8LCQDDCBzoPbtlvHQkhKhgRSiR+bS4TMTCEm8l639XzuIjXu
 MFezVlH31+tZAPqbRk4YJvoNqQuUCAhMWLYx6XOCOQonMZ5eyDto/5hAUGGKV9Cn
 aQjCTsVB5/ngZjz6gVYR
 =pM5V
 -----END PGP SIGNATURE-----

Merge tag 'hisi-arm64-dt-for-5.11' of git://github.com/hisilicon/linux-hisi into arm/dt

ARM64: DT: Hisilicon ARM64 DT updates for 5.11

- Cleanups of the hisilicon DTS to align with the dtschema. All of them do not
  have any functional effect except passing dtschema checks or dtc W=2 builds.

* tag 'hisi-arm64-dt-for-5.11' of git://github.com/hisilicon/linux-hisi:
  arm64: dts: hisilicon: Use generic "ngpios" rather than "snps,nr-gpios"
  arm64: dts: hi3660: Harmonize DWC USB3 DT nodes name
  arm64: dts: hisilicon: list all clocks required by snps-dw-apb-uart.yaml
  arm64: dts: hisilicon: list all clocks required by pl011.yaml
  arm64: dts: hisilicon: list all clocks required by spi-pl022.yaml
  arm64: dts: hisilicon: normalize the node name of the UART devices
  arm64: dts: hisilicon: normalize the node name of the usb devices
  arm64: dts: hisilicon: normalize the node name of the SMMU devices
  arm64: dts: hisilicon: place clock-names "biu" before "ciu"
  arm64: dts: hisilicon: remove unused property pinctrl-names
  arm64: dts: hisilicon: write the values of property-units into a uint32 array
  arm64: dts: hisilicon: separate each group of data in the property "reg"
  arm64: dts: hisilicon: normalize the node name of the ITS devices

Link: https://lore.kernel.org/r/5FBDC416.5060008@hisilicon.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
This commit is contained in:
Arnd Bergmann 2020-11-26 22:11:52 +01:00
commit 2df8aa0373
7 changed files with 132 additions and 133 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
arch/arm64/boot/dts/hisilicon/hi3660.dtsi
View File

@ -971,8 +971,8 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>;
clock-names = "apb_pclk";
clocks = <&crg_ctrl HI3660_CLK_GATE_SPI2>, <&crg_ctrl HI3660_CLK_GATE_SPI2>;
clock-names = "sspclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&spi2_pmx_func &spi2_cfg_func>;
num-cs = <1>;
@ -986,8 +986,8 @@
#address-cells = <1>;
#size-cells = <0>;
interrupts = <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>;
clock-names = "apb_pclk";
clocks = <&crg_ctrl HI3660_CLK_GATE_SPI3>, <&crg_ctrl HI3660_CLK_GATE_SPI3>;
clock-names = "sspclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&spi3_pmx_func &spi3_cfg_func>;
num-cs = <1>;
@ -1045,7 +1045,8 @@
clocks = <&crg_ctrl HI3660_CLK_GATE_UFSIO_REF>,
<&crg_ctrl HI3660_CLK_GATE_UFSPHY_CFG>;
clock-names = "ref_clk", "phy_clk";
freq-table-hz = <0 0>, <0 0>;
freq-table-hz = <0 0
0 0>;
/* offset: 0x84; bit: 12 */
resets = <&crg_rst 0x84 12>;
reset-names = "rst";
@ -1168,7 +1169,7 @@
};
};
dwc3: dwc3@ff100000 {
dwc3: usb@ff100000 {
compatible = "snps,dwc3";
reg = <0x0 0xff100000 0x0 0x100000>;

5
arch/arm64/boot/dts/hisilicon/hi3670.dtsi
View File

@ -213,7 +213,6 @@
clocks = <&crg_ctrl HI3670_CLK_GATE_UART1>,
<&crg_ctrl HI3670_PCLK>;
clock-names = "uartclk", "apb_pclk";
pinctrl-names = "default";
status = "disabled";
};
@ -260,7 +259,6 @@
clocks = <&crg_ctrl HI3670_CLK_GATE_UART5>,
<&crg_ctrl HI3670_PCLK>;
clock-names = "uartclk", "apb_pclk";
pinctrl-names = "default";
status = "disabled";
};
@ -667,7 +665,8 @@
clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>,
<&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>;
clock-names = "ref_clk", "phy_clk";
freq-table-hz = <0 0>, <0 0>;
freq-table-hz = <0 0
0 0>;
/* offset: 0x84; bit: 12 */
resets = <&crg_rst 0x84 12>;
reset-names = "rst";

27
arch/arm64/boot/dts/hisilicon/hi3798cv200.dtsi
View File

@ -91,11 +91,10 @@
gmacphyrst: reset-controller {
compatible = "ti,syscon-reset";
#reset-cells = <1>;
ti,reset-bits =
<0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR |
DEASSERT_SET|STATUS_NONE)>,
<0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR |
DEASSERT_SET|STATUS_NONE)>;
ti,reset-bits = <
0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR | DEASSERT_SET | STATUS_NONE)
0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR | DEASSERT_SET | STATUS_NONE)
>;
};
};
@ -217,8 +216,8 @@
compatible = "arm,pl011", "arm,primecell";
reg = <0x8b00000 0x1000>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sysctrl HISTB_UART0_CLK>;
clock-names = "apb_pclk";
clocks = <&sysctrl HISTB_UART0_CLK>, <&sysctrl HISTB_UART0_CLK>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
@ -226,8 +225,8 @@
compatible = "arm,pl011", "arm,primecell";
reg = <0x8b02000 0x1000>;
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HISTB_UART2_CLK>;
clock-names = "apb_pclk";
clocks = <&crg HISTB_UART2_CLK>, <&crg HISTB_UART2_CLK>;
clock-names = "uartclk", "apb_pclk";
status = "disabled";
};
@ -292,8 +291,8 @@
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
num-cs = <1>;
cs-gpios = <&gpio7 1 0>;
clocks = <&crg HISTB_SPI0_CLK>;
clock-names = "apb_pclk";
clocks = <&crg HISTB_SPI0_CLK>, <&crg HISTB_SPI0_CLK>;
clock-names = "sspclk", "apb_pclk";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@ -305,7 +304,7 @@
interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&crg HISTB_SDIO0_CIU_CLK>,
<&crg HISTB_SDIO0_BIU_CLK>;
clock-names = "ciu", "biu";
clock-names = "biu", "ciu";
resets = <&crg 0x9c 4>;
reset-names = "reset";
status = "disabled";
@ -585,7 +584,7 @@
status = "disabled";
};
ohci: ohci@9880000 {
ohci: usb@9880000 {
compatible = "generic-ohci";
reg = <0x9880000 0x10000>;
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
@ -600,7 +599,7 @@
status = "disabled";
};
ehci: ehci@9890000 {
ehci: usb@9890000 {
compatible = "generic-ehci";
reg = <0x9890000 0x10000>;
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;

4
arch/arm64/boot/dts/hisilicon/hi6220.dtsi
View File

@ -725,8 +725,8 @@
interrupts = <0 50 4>;
bus-id = <0>;
enable-dma = <0>;
clocks = <&sys_ctrl HI6220_SPI_CLK>;
clock-names = "apb_pclk";
clocks = <&sys_ctrl HI6220_SPI_CLK>, <&sys_ctrl HI6220_SPI_CLK>;
clock-names = "sspclk", "apb_pclk";
pinctrl-names = "default";
pinctrl-0 = <&spi0_pmx_func &spi0_cfg_func>;
num-cs = <1>;

24
arch/arm64/boot/dts/hisilicon/hip05.dtsi
View File

@ -242,28 +242,28 @@
<0x0 0xfe020000 0 0x10000>; /* GICV */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
its_peri: interrupt-controller@8c000000 {
its_peri: msi-controller@8c000000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x0 0x8c000000 0x0 0x40000>;
};
its_m3: interrupt-controller@a3000000 {
its_m3: msi-controller@a3000000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x0 0xa3000000 0x0 0x40000>;
};
its_pcie: interrupt-controller@b7000000 {
its_pcie: msi-controller@b7000000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x0 0xb7000000 0x0 0x40000>;
};
its_dsa: interrupt-controller@c6000000 {
its_dsa: msi-controller@c6000000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
@ -296,23 +296,23 @@
clock-frequency = <200000000>;
};
uart0: uart@80300000 {
uart0: serial@80300000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x80300000 0x0 0x10000>;
interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&refclk200mhz>;
clock-names = "apb_pclk";
clocks = <&refclk200mhz>, <&refclk200mhz>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
};
uart1: uart@80310000 {
uart1: serial@80310000 {
compatible = "snps,dw-apb-uart";
reg = <0x0 0x80310000 0x0 0x10000>;
interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&refclk200mhz>;
clock-names = "apb_pclk";
clocks = <&refclk200mhz>, <&refclk200mhz>;
clock-names = "baudclk", "apb_pclk";
reg-shift = <2>;
reg-io-width = <4>;
status = "disabled";
@ -335,7 +335,7 @@
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <32>;
ngpios = <32>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;
@ -354,7 +354,7 @@
compatible = "snps,dw-apb-gpio-port";
gpio-controller;
#gpio-cells = <2>;
snps,nr-gpios = <32>;
ngpios = <32>;
reg = <0>;
interrupt-controller;
#interrupt-cells = <2>;

14
arch/arm64/boot/dts/hisilicon/hip06.dtsi
View File

@ -242,7 +242,7 @@
<0x0 0xfe020000 0 0x10000>; /* GICV */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
its_dsa: interrupt-controller@c6000000 {
its_dsa: msi-controller@c6000000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
@ -330,7 +330,7 @@
* when iommu-map entry is used along with the PCIe node.
* Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html
*/
smmu0: smmu_pcie {
smmu0: iommu@a0040000 {
compatible = "arm,smmu-v3";
reg = <0x0 0xa0040000 0x0 0x20000>;
#iommu-cells = <1>;
@ -359,7 +359,7 @@
status = "disabled";
};
uart0: lpc-uart@2f8 {
uart0: serial@2f8 {
compatible = "ns16550a";
clock-frequency = <1843200>;
reg = <0x01 0x2f8 0x08>;
@ -373,7 +373,7 @@
#clock-cells = <0>;
};
usb_ohci: ohci@a7030000 {
usb_ohci: usb@a7030000 {
compatible = "generic-ohci";
reg = <0x0 0xa7030000 0x0 0x10000>;
interrupt-parent = <&mbigen_usb>;
@ -382,7 +382,7 @@
status = "disabled";
};
usb_ehci: ehci@a7020000 {
usb_ehci: usb@a7020000 {
compatible = "generic-ehci";
reg = <0x0 0xa7020000 0x0 0x10000>;
interrupt-parent = <&mbigen_usb>;
@ -434,8 +434,8 @@
#size-cells = <0>;
compatible = "hisilicon,hns-dsaf-v2";
mode = "6port-16rss";
reg = <0x0 0xc5000000 0x0 0x890000
0x0 0xc7000000 0x0 0x600000>;
reg = <0x0 0xc5000000 0x0 0x890000>,
<0x0 0xc7000000 0x0 0x600000>;
reg-names = "ppe-base", "dsaf-base";
interrupt-parent = <&mbigen_dsaf0>;
subctrl-syscon = <&dsa_subctrl>;

178
arch/arm64/boot/dts/hisilicon/hip07.dtsi
View File

@ -924,56 +924,56 @@
<0x0 0xfe020000 0x0 0x10000>; /* GICV */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
p0_its_peri_a: interrupt-controller@4c000000 {
p0_its_peri_a: msi-controller@4c000000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x0 0x4c000000 0x0 0x40000>;
};
p0_its_peri_b: interrupt-controller@6c000000 {
p0_its_peri_b: msi-controller@6c000000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x0 0x6c000000 0x0 0x40000>;
};
p0_its_dsa_a: interrupt-controller@c6000000 {
p0_its_dsa_a: msi-controller@c6000000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x0 0xc6000000 0x0 0x40000>;
};
p0_its_dsa_b: interrupt-controller@8,c6000000 {
p0_its_dsa_b: msi-controller@8c6000000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x8 0xc6000000 0x0 0x40000>;
};
p1_its_peri_a: interrupt-controller@400,4c000000 {
p1_its_peri_a: msi-controller@4004c000000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x400 0x4c000000 0x0 0x40000>;
};
p1_its_peri_b: interrupt-controller@400,6c000000 {
p1_its_peri_b: msi-controller@4006c000000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x400 0x6c000000 0x0 0x40000>;
};
p1_its_dsa_a: interrupt-controller@400,c6000000 {
p1_its_dsa_a: msi-controller@400c6000000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
reg = <0x400 0xc6000000 0x0 0x40000>;
};
p1_its_dsa_b: interrupt-controller@408,c6000000 {
p1_its_dsa_b: msi-controller@408c6000000 {
compatible = "arm,gic-v3-its";
msi-controller;
#msi-cells = <1>;
@ -1161,7 +1161,7 @@
* when iommu-map entry is used along with the PCIe node.
* Refer:https://www.spinics.net/lists/arm-kernel/msg602812.html
*/
smmu0: smmu_pcie {
smmu0: iommu@a0040000 {
compatible = "arm,smmu-v3";
reg = <0x0 0xa0040000 0x0 0x20000>;
#iommu-cells = <1>;
@ -1170,7 +1170,7 @@
hisilicon,broken-prefetch-cmd;
status = "disabled";
};
p0_smmu_alg_a: smmu_alg@d0040000 {
p0_smmu_alg_a: iommu@d0040000 {
compatible = "arm,smmu-v3";
reg = <0x0 0xd0040000 0x0 0x20000>;
interrupt-parent = <&p0_mbigen_smmu_alg_a>;
@ -1183,7 +1183,7 @@
hisilicon,broken-prefetch-cmd;
/* smmu-cb-memtype = <0x0 0x1>;*/
};
p0_smmu_alg_b: smmu_alg@8,d0040000 {
p0_smmu_alg_b: iommu@8d0040000 {
compatible = "arm,smmu-v3";
reg = <0x8 0xd0040000 0x0 0x20000>;
interrupt-parent = <&p0_mbigen_smmu_alg_b>;
@ -1196,7 +1196,7 @@
hisilicon,broken-prefetch-cmd;
/* smmu-cb-memtype = <0x0 0x1>;*/
};
p1_smmu_alg_a: smmu_alg@400,d0040000 {
p1_smmu_alg_a: iommu@400d0040000 {
compatible = "arm,smmu-v3";
reg = <0x400 0xd0040000 0x0 0x20000>;
interrupt-parent = <&p1_mbigen_smmu_alg_a>;
@ -1209,7 +1209,7 @@
hisilicon,broken-prefetch-cmd;
/* smmu-cb-memtype = <0x0 0x1>;*/
};
p1_smmu_alg_b: smmu_alg@408,d0040000 {
p1_smmu_alg_b: iommu@408d0040000 {
compatible = "arm,smmu-v3";
reg = <0x408 0xd0040000 0x0 0x20000>;
interrupt-parent = <&p1_mbigen_smmu_alg_b>;
@ -1253,7 +1253,7 @@
status = "disabled";
};
usb_ohci: ohci@a7030000 {
usb_ohci: usb@a7030000 {
compatible = "generic-ohci";
reg = <0x0 0xa7030000 0x0 0x10000>;
interrupt-parent = <&mbigen_usb>;
@ -1262,7 +1262,7 @@
status = "disabled";
};
usb_ehci: ehci@a7020000 {
usb_ehci: usb@a7020000 {
compatible = "generic-ehci";
reg = <0x0 0xa7020000 0x0 0x10000>;
interrupt-parent = <&mbigen_usb>;
@ -1321,8 +1321,8 @@
#size-cells = <0>;
compatible = "hisilicon,hns-dsaf-v2";
mode = "6port-16rss";
reg = <0x0 0xc5000000 0x0 0x890000
0x0 0xc7000000 0x0 0x600000>;
reg = <0x0 0xc5000000 0x0 0x890000>,
<0x0 0xc7000000 0x0 0x600000>;
reg-names = "ppe-base", "dsaf-base";
interrupt-parent = <&mbigen_dsaf0>;
subctrl-syscon = <&dsa_subctrl>;
@ -1720,24 +1720,24 @@
};
p0_sec_a: crypto@d2000000 {
compatible = "hisilicon,hip07-sec";
reg = <0x0 0xd0000000 0x0 0x10000
0x0 0xd2000000 0x0 0x10000
0x0 0xd2010000 0x0 0x10000
0x0 0xd2020000 0x0 0x10000
0x0 0xd2030000 0x0 0x10000
0x0 0xd2040000 0x0 0x10000
0x0 0xd2050000 0x0 0x10000
0x0 0xd2060000 0x0 0x10000
0x0 0xd2070000 0x0 0x10000
0x0 0xd2080000 0x0 0x10000
0x0 0xd2090000 0x0 0x10000
0x0 0xd20a0000 0x0 0x10000
0x0 0xd20b0000 0x0 0x10000
0x0 0xd20c0000 0x0 0x10000
0x0 0xd20d0000 0x0 0x10000
0x0 0xd20e0000 0x0 0x10000
0x0 0xd20f0000 0x0 0x10000
0x0 0xd2100000 0x0 0x10000>;
reg = <0x0 0xd0000000 0x0 0x10000>,
<0x0 0xd2000000 0x0 0x10000>,
<0x0 0xd2010000 0x0 0x10000>,
<0x0 0xd2020000 0x0 0x10000>,
<0x0 0xd2030000 0x0 0x10000>,
<0x0 0xd2040000 0x0 0x10000>,
<0x0 0xd2050000 0x0 0x10000>,
<0x0 0xd2060000 0x0 0x10000>,
<0x0 0xd2070000 0x0 0x10000>,
<0x0 0xd2080000 0x0 0x10000>,
<0x0 0xd2090000 0x0 0x10000>,
<0x0 0xd20a0000 0x0 0x10000>,
<0x0 0xd20b0000 0x0 0x10000>,
<0x0 0xd20c0000 0x0 0x10000>,
<0x0 0xd20d0000 0x0 0x10000>,
<0x0 0xd20e0000 0x0 0x10000>,
<0x0 0xd20f0000 0x0 0x10000>,
<0x0 0xd2100000 0x0 0x10000>;
interrupt-parent = <&p0_mbigen_sec_a>;
iommus = <&p0_smmu_alg_a 0x600>;
dma-coherent;
@ -1761,24 +1761,24 @@
};
p0_sec_b: crypto@8,d2000000 {
compatible = "hisilicon,hip07-sec";
reg = <0x8 0xd0000000 0x0 0x10000
0x8 0xd2000000 0x0 0x10000
0x8 0xd2010000 0x0 0x10000
0x8 0xd2020000 0x0 0x10000
0x8 0xd2030000 0x0 0x10000
0x8 0xd2040000 0x0 0x10000
0x8 0xd2050000 0x0 0x10000
0x8 0xd2060000 0x0 0x10000
0x8 0xd2070000 0x0 0x10000
0x8 0xd2080000 0x0 0x10000
0x8 0xd2090000 0x0 0x10000
0x8 0xd20a0000 0x0 0x10000
0x8 0xd20b0000 0x0 0x10000
0x8 0xd20c0000 0x0 0x10000
0x8 0xd20d0000 0x0 0x10000
0x8 0xd20e0000 0x0 0x10000
0x8 0xd20f0000 0x0 0x10000
0x8 0xd2100000 0x0 0x10000>;
reg = <0x8 0xd0000000 0x0 0x10000>,
<0x8 0xd2000000 0x0 0x10000>,
<0x8 0xd2010000 0x0 0x10000>,
<0x8 0xd2020000 0x0 0x10000>,
<0x8 0xd2030000 0x0 0x10000>,
<0x8 0xd2040000 0x0 0x10000>,
<0x8 0xd2050000 0x0 0x10000>,
<0x8 0xd2060000 0x0 0x10000>,
<0x8 0xd2070000 0x0 0x10000>,
<0x8 0xd2080000 0x0 0x10000>,
<0x8 0xd2090000 0x0 0x10000>,
<0x8 0xd20a0000 0x0 0x10000>,
<0x8 0xd20b0000 0x0 0x10000>,
<0x8 0xd20c0000 0x0 0x10000>,
<0x8 0xd20d0000 0x0 0x10000>,
<0x8 0xd20e0000 0x0 0x10000>,
<0x8 0xd20f0000 0x0 0x10000>,
<0x8 0xd2100000 0x0 0x10000>;
interrupt-parent = <&p0_mbigen_sec_b>;
iommus = <&p0_smmu_alg_b 0x600>;
dma-coherent;
@ -1802,24 +1802,24 @@
};
p1_sec_a: crypto@400,d2000000 {
compatible = "hisilicon,hip07-sec";
reg = <0x400 0xd0000000 0x0 0x10000
0x400 0xd2000000 0x0 0x10000
0x400 0xd2010000 0x0 0x10000
0x400 0xd2020000 0x0 0x10000
0x400 0xd2030000 0x0 0x10000
0x400 0xd2040000 0x0 0x10000
0x400 0xd2050000 0x0 0x10000
0x400 0xd2060000 0x0 0x10000
0x400 0xd2070000 0x0 0x10000
0x400 0xd2080000 0x0 0x10000
0x400 0xd2090000 0x0 0x10000
0x400 0xd20a0000 0x0 0x10000
0x400 0xd20b0000 0x0 0x10000
0x400 0xd20c0000 0x0 0x10000
0x400 0xd20d0000 0x0 0x10000
0x400 0xd20e0000 0x0 0x10000
0x400 0xd20f0000 0x0 0x10000
0x400 0xd2100000 0x0 0x10000>;
reg = <0x400 0xd0000000 0x0 0x10000>,
<0x400 0xd2000000 0x0 0x10000>,
<0x400 0xd2010000 0x0 0x10000>,
<0x400 0xd2020000 0x0 0x10000>,
<0x400 0xd2030000 0x0 0x10000>,
<0x400 0xd2040000 0x0 0x10000>,
<0x400 0xd2050000 0x0 0x10000>,
<0x400 0xd2060000 0x0 0x10000>,
<0x400 0xd2070000 0x0 0x10000>,
<0x400 0xd2080000 0x0 0x10000>,
<0x400 0xd2090000 0x0 0x10000>,
<0x400 0xd20a0000 0x0 0x10000>,
<0x400 0xd20b0000 0x0 0x10000>,
<0x400 0xd20c0000 0x0 0x10000>,
<0x400 0xd20d0000 0x0 0x10000>,
<0x400 0xd20e0000 0x0 0x10000>,
<0x400 0xd20f0000 0x0 0x10000>,
<0x400 0xd2100000 0x0 0x10000>;
interrupt-parent = <&p1_mbigen_sec_a>;
iommus = <&p1_smmu_alg_a 0x600>;
dma-coherent;
@ -1843,24 +1843,24 @@
};
p1_sec_b: crypto@408,d2000000 {
compatible = "hisilicon,hip07-sec";
reg = <0x408 0xd0000000 0x0 0x10000
0x408 0xd2000000 0x0 0x10000
0x408 0xd2010000 0x0 0x10000
0x408 0xd2020000 0x0 0x10000
0x408 0xd2030000 0x0 0x10000
0x408 0xd2040000 0x0 0x10000
0x408 0xd2050000 0x0 0x10000
0x408 0xd2060000 0x0 0x10000
0x408 0xd2070000 0x0 0x10000
0x408 0xd2080000 0x0 0x10000
0x408 0xd2090000 0x0 0x10000
0x408 0xd20a0000 0x0 0x10000
0x408 0xd20b0000 0x0 0x10000
0x408 0xd20c0000 0x0 0x10000
0x408 0xd20d0000 0x0 0x10000
0x408 0xd20e0000 0x0 0x10000
0x408 0xd20f0000 0x0 0x10000
0x408 0xd2100000 0x0 0x10000>;
reg = <0x408 0xd0000000 0x0 0x10000>,
<0x408 0xd2000000 0x0 0x10000>,
<0x408 0xd2010000 0x0 0x10000>,
<0x408 0xd2020000 0x0 0x10000>,
<0x408 0xd2030000 0x0 0x10000>,
<0x408 0xd2040000 0x0 0x10000>,
<0x408 0xd2050000 0x0 0x10000>,
<0x408 0xd2060000 0x0 0x10000>,
<0x408 0xd2070000 0x0 0x10000>,
<0x408 0xd2080000 0x0 0x10000>,
<0x408 0xd2090000 0x0 0x10000>,
<0x408 0xd20a0000 0x0 0x10000>,
<0x408 0xd20b0000 0x0 0x10000>,
<0x408 0xd20c0000 0x0 0x10000>,
<0x408 0xd20d0000 0x0 0x10000>,
<0x408 0xd20e0000 0x0 0x10000>,
<0x408 0xd20f0000 0x0 0x10000>,
<0x408 0xd2100000 0x0 0x10000>;
interrupt-parent = <&p1_mbigen_sec_b>;
iommus = <&p1_smmu_alg_b 0x600>;
dma-coherent;