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can: sja1000: Add Quirk for RZ/N1 SJA1000 CAN controller

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As per Chapter 6.5.16 of the RZ/N1 Peripheral Manual, The SJA1000
CAN controller does not support Clock Divider Register compared to
the reference Philips SJA1000 device.

This patch adds a device quirk to handle this difference.

Link: https://lore.kernel.org/all/20220710115248.190280-4-biju.das.jz@bp.renesas.com
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
This commit is contained in:
Biju Das 2022-07-10 12:52:45 +01:00 committed by Marc Kleine-Budde
parent 4591c760b7
commit 2d99bfbf33
2 changed files with 7 additions and 4 deletions
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8
drivers/net/can/sja1000/sja1000.c
View File

@ -183,8 +183,9 @@ static void chipset_init(struct net_device *dev)
{
struct sja1000_priv *priv = netdev_priv(dev);
/* set clock divider and output control register */
priv->write_reg(priv, SJA1000_CDR, priv->cdr | CDR_PELICAN);
if (!(priv->flags & SJA1000_QUIRK_NO_CDR_REG))
/* set clock divider and output control register */
priv->write_reg(priv, SJA1000_CDR, priv->cdr | CDR_PELICAN);
/* set acceptance filter (accept all) */
priv->write_reg(priv, SJA1000_ACCC0, 0x00);
@ -209,7 +210,8 @@ static void sja1000_start(struct net_device *dev)
set_reset_mode(dev);
/* Initialize chip if uninitialized at this stage */
if (!(priv->read_reg(priv, SJA1000_CDR) & CDR_PELICAN))
if (!(priv->flags & SJA1000_QUIRK_NO_CDR_REG ||
priv->read_reg(priv, SJA1000_CDR) & CDR_PELICAN))
chipset_init(dev);
/* Clear error counters and error code capture */

3
drivers/net/can/sja1000/sja1000.h
View File

@ -145,7 +145,8 @@
/*
* Flags for sja1000priv.flags
*/
#define SJA1000_CUSTOM_IRQ_HANDLER 0x1
#define SJA1000_CUSTOM_IRQ_HANDLER BIT(0)
#define SJA1000_QUIRK_NO_CDR_REG BIT(1)
/*
* SJA1000 private data structure