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dt-bindings: arm: Drop the non-YAML bindings
We created new bindings for the ARM Board using YAML so delete the old human-parseable-only bindings. Cc: Sudeep Holla <sudeep.holla@arm.com> Reviewed-by: Rob Herring <robh@kernel.org> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This commit is contained in:
Linus Walleij
parent
4fb00d9066
commit
2d483550b6
@ -1,237 +0,0 @@
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ARM Integrator/AP (Application Platform) and Integrator/CP (Compact Platform)
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-----------------------------------------------------------------------------
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ARM's oldest Linux-supported platform with connectors for different core
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tiles of ARMv4, ARMv5 and ARMv6 type.
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Required properties (in root node):
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compatible = "arm,integrator-ap"; /* Application Platform */
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compatible = "arm,integrator-cp"; /* Compact Platform */
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FPGA type interrupt controllers, see the versatile-fpga-irq binding doc.
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Required nodes:
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- core-module: the root node to the Integrator platforms must have
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a core-module with regs and the compatible string
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"arm,core-module-integrator"
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- external-bus-interface: the root node to the Integrator platforms
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must have an external bus interface with regs and the
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compatible-string "arm,external-bus-interface"
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Required properties for the core module:
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- regs: the location and size of the core module registers, one
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range of 0x200 bytes.
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- syscon: the root node of the Integrator platforms must have a
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system controller node pointing to the control registers,
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with the compatible string
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"arm,integrator-ap-syscon"
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"arm,integrator-cp-syscon"
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respectively.
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Required properties for the system controller:
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- regs: the location and size of the system controller registers,
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one range of 0x100 bytes.
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Required properties for the AP system controller:
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- interrupts: the AP syscon node must include the logical module
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interrupts, stated in order of module instance <module 0>,
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<module 1>, <module 2> ... for the CP system controller this
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is not required not of any use.
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/dts-v1/;
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/include/ "integrator.dtsi"
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/ {
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model = "ARM Integrator/AP";
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compatible = "arm,integrator-ap";
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core-module@10000000 {
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compatible = "arm,core-module-integrator";
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reg = <0x10000000 0x200>;
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};
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ebi@12000000 {
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compatible = "arm,external-bus-interface";
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reg = <0x12000000 0x100>;
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};
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syscon {
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compatible = "arm,integrator-ap-syscon";
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reg = <0x11000000 0x100>;
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interrupt-parent = <&pic>;
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/* These are the logic module IRQs */
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interrupts = <9>, <10>, <11>, <12>;
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};
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};
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ARM Versatile Application and Platform Baseboards
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-------------------------------------------------
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ARM's development hardware platform with connectors for customizable
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core tiles. The hardware configuration of the Versatile boards is
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highly customizable.
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Required properties (in root node):
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compatible = "arm,versatile-ab"; /* Application baseboard */
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compatible = "arm,versatile-pb"; /* Platform baseboard */
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Interrupt controllers:
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- VIC required properties:
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compatible = "arm,versatile-vic";
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interrupt-controller;
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#interrupt-cells = <1>;
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- SIC required properties:
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compatible = "arm,versatile-sic";
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interrupt-controller;
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#interrupt-cells = <1>;
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Required nodes:
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- core-module: the root node to the Versatile platforms must have
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a core-module with regs and the compatible strings
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"arm,core-module-versatile", "syscon"
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Optional nodes:
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- arm,versatile-ib2-syscon : if the Versatile has an IB2 interface
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board mounted, this has a separate system controller that is
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defined in this node.
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Required properties:
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compatible = "arm,versatile-ib2-syscon", "syscon"
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ARM RealView Boards
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-------------------
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The RealView boards cover tailored evaluation boards that are used to explore
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the ARM11 and Cortex A-8 and Cortex A-9 processors.
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Required properties (in root node):
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/* RealView Emulation Baseboard */
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compatible = "arm,realview-eb";
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/* RealView Platform Baseboard for ARM1176JZF-S */
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compatible = "arm,realview-pb1176";
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/* RealView Platform Baseboard for ARM11 MPCore */
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compatible = "arm,realview-pb11mp";
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/* RealView Platform Baseboard for Cortex A-8 */
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compatible = "arm,realview-pba8";
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/* RealView Platform Baseboard Explore for Cortex A-9 */
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compatible = "arm,realview-pbx";
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Required nodes:
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- soc: some node of the RealView platforms must be the SoC
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node that contain the SoC-specific devices, with the compatible
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string set to one of these tuples:
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"arm,realview-eb-soc", "simple-bus"
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"arm,realview-pb1176-soc", "simple-bus"
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"arm,realview-pb11mp-soc", "simple-bus"
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"arm,realview-pba8-soc", "simple-bus"
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"arm,realview-pbx-soc", "simple-bus"
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- syscon: some subnode of the RealView SoC node must be a
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system controller node pointing to the control registers,
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with the compatible string set to one of these:
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"arm,realview-eb11mp-revb-syscon", "arm,realview-eb-syscon", "syscon"
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"arm,realview-eb11mp-revc-syscon", "arm,realview-eb-syscon", "syscon"
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"arm,realview-eb-syscon", "syscon"
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"arm,realview-pb1176-syscon", "syscon"
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"arm,realview-pb11mp-syscon", "syscon"
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"arm,realview-pba8-syscon", "syscon"
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"arm,realview-pbx-syscon", "syscon"
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Required properties for the system controller:
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- regs: the location and size of the system controller registers,
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one range of 0x1000 bytes.
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Example:
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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model = "ARM RealView PB1176 with device tree";
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compatible = "arm,realview-pb1176";
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#address-cells = <1>;
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#size-cells = <1>;
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "arm,realview-pb1176-soc", "simple-bus";
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ranges;
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syscon: syscon@10000000 {
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compatible = "arm,realview-syscon", "syscon";
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reg = <0x10000000 0x1000>;
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};
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};
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};
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ARM Versatile Express Boards
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-----------------------------
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For details on the device tree bindings for ARM Versatile Express boards
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please consult the vexpress.txt file in the same directory as this file.
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ARM Juno Boards
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----------------
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The Juno boards are targeting development for AArch64 systems. The first
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iteration, Juno r0, is a vehicle for evaluating big.LITTLE on AArch64,
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with the second iteration, Juno r1, mainly aimed at development of PCIe
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based systems. Juno r1 also has support for AXI masters placed on the TLX
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connectors to join the coherency domain.
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Juno boards are described in a similar way to ARM Versatile Express boards,
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with the motherboard part of the hardware being described in a separate file
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to highlight the fact that is part of the support infrastructure for the SoC.
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Juno device tree bindings also share the Versatile Express bindings as
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described under the RS1 memory mapping.
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Required properties (in root node):
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compatible = "arm,juno"; /* For Juno r0 board */
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compatible = "arm,juno-r1"; /* For Juno r1 board */
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compatible = "arm,juno-r2"; /* For Juno r2 board */
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Required nodes:
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The description for the board must include:
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- a "psci" node describing the boot method used for the secondary CPUs.
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A detailed description of the bindings used for "psci" nodes is present
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in the psci.yaml file.
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- a "cpus" node describing the available cores and their associated
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"enable-method"s. For more details see cpus.yaml file.
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Example:
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/dts-v1/;
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/ {
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model = "ARM Juno development board (r0)";
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compatible = "arm,juno", "arm,vexpress";
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interrupt-parent = <&gic>;
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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A57_0: cpu@0 {
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compatible = "arm,cortex-a57";
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reg = <0x0 0x0>;
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device_type = "cpu";
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enable-method = "psci";
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};
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.....
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A53_0: cpu@100 {
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compatible = "arm,cortex-a53";
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reg = <0x0 0x100>;
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device_type = "cpu";
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enable-method = "psci";
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};
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.....
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};
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};
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@ -1,229 +0,0 @@
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ARM Versatile Express boards family
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-----------------------------------
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ARM's Versatile Express platform consists of a motherboard and one
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or more daughterboards (tiles). The motherboard provides a set of
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peripherals. Processor and RAM "live" on the tiles.
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The motherboard and each core tile should be described by a separate
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Device Tree source file, with the tile's description including
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the motherboard file using a /include/ directive. As the motherboard
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can be initialized in one of two different configurations ("memory
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maps"), care must be taken to include the correct one.
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Root node
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---------
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Required properties in the root node:
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- compatible value:
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compatible = "arm,vexpress,<model>", "arm,vexpress";
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where <model> is the full tile model name (as used in the tile's
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Technical Reference Manual), eg.:
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- for Coretile Express A5x2 (V2P-CA5s):
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compatible = "arm,vexpress,v2p-ca5s", "arm,vexpress";
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- for Coretile Express A9x4 (V2P-CA9):
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compatible = "arm,vexpress,v2p-ca9", "arm,vexpress";
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If a tile comes in several variants or can be used in more then one
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configuration, the compatible value should be:
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compatible = "arm,vexpress,<model>,<variant>", \
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"arm,vexpress,<model>", "arm,vexpress";
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eg:
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- Coretile Express A15x2 (V2P-CA15) with Tech Chip 1:
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compatible = "arm,vexpress,v2p-ca15,tc1", \
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"arm,vexpress,v2p-ca15", "arm,vexpress";
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- LogicTile Express 13MG (V2F-2XV6) running Cortex-A7 (3 cores) SMM:
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compatible = "arm,vexpress,v2f-2xv6,ca7x3", \
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"arm,vexpress,v2f-2xv6", "arm,vexpress";
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Optional properties in the root node:
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- tile model name (use name from the tile's Technical Reference
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Manual, eg. "V2P-CA5s")
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model = "<model>";
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- tile's HBI number (unique ARM's board model ID, visible on the
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PCB's silkscreen) in hexadecimal transcription:
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arm,hbi = <0xhbi>
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eg:
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- for Coretile Express A5x2 (V2P-CA5s) HBI-0191:
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arm,hbi = <0x191>;
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- Coretile Express A9x4 (V2P-CA9) HBI-0225:
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arm,hbi = <0x225>;
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CPU nodes
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---------
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Top-level standard "cpus" node is required. It must contain a node
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with device_type = "cpu" property for every available core, eg.:
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a5";
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reg = <0>;
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};
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};
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Configuration infrastructure
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----------------------------
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The platform has an elaborated configuration system, consisting of
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microcontrollers residing on the mother- and daughterboards known
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as Motherboard/Daughterboard Configuration Controller (MCC and DCC).
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The controllers are responsible for the platform initialization
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(reset generation, flash programming, FPGA bitfiles loading etc.)
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but also control clock generators, voltage regulators, gather
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environmental data like temperature, power consumption etc. Even
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the video output switch (FPGA) is controlled that way.
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The controllers are not mapped into normal memory address space
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and must be accessed through bridges - other devices capable
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of generating transactions on the configuration bus.
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The nodes describing configuration controllers must define
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the following properties:
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- compatible value:
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compatible = "arm,vexpress,config-bus";
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- bridge phandle:
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arm,vexpress,config-bridge = <phandle>;
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and children describing available functions.
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Platform topology
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-----------------
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As Versatile Express can be configured in number of physically
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different setups, the device tree should describe platform topology.
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Root node and main motherboard node must define the following
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property, describing physical location of the children nodes:
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- site number:
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arm,vexpress,site = <number>;
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where 0 means motherboard, 1 or 2 are daugtherboard sites,
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0xf means "master" site (site containing main CPU tile)
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- when daughterboards are stacked on one site, their position
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in the stack be be described with:
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arm,vexpress,position = <number>;
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- when describing tiles consisting more than one DCC, its number
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can be described with:
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arm,vexpress,dcc = <number>;
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Any of the numbers above defaults to zero if not defined in
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the node or any of its parent.
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Motherboard
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-----------
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The motherboard description file provides a single "motherboard" node
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using 2 address cells corresponding to the Static Memory Bus used
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between the motherboard and the tile. The first cell defines the Chip
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Select (CS) line number, the second cell address offset within the CS.
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All interrupt lines between the motherboard and the tile are active
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high and are described using single cell.
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Optional properties of the "motherboard" node:
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- motherboard's memory map variant:
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arm,v2m-memory-map = "<name>";
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where name is one of:
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- "rs1" - for RS1 map (i.a. peripherals on CS3); this map is also
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referred to as "ARM Cortex-A Series memory map":
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arm,v2m-memory-map = "rs1";
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When this property is missing, the motherboard is using the original
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memory map (also known as the "Legacy memory map", primarily used
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with the original CoreTile Express A9x4) with peripherals on CS7.
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Motherboard .dtsi files provide a set of labelled peripherals that
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can be used to obtain required phandle in the tile's "aliases" node:
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- UARTs, note that the numbers correspond to the physical connectors
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on the motherboard's back panel:
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v2m_serial0, v2m_serial1, v2m_serial2 and v2m_serial3
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- I2C controllers:
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v2m_i2c_dvi and v2m_i2c_pcie
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- SP804 timers:
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v2m_timer01 and v2m_timer23
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The tile description should define a "smb" node, describing the
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Static Memory Bus between the tile and motherboard. It must define
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the following properties:
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- "simple-bus" compatible value (to ensure creation of the children)
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compatible = "simple-bus";
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- mapping of the SMB CS/offset addresses into main address space:
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#address-cells = <2>;
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#size-cells = <1>;
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ranges = <...>;
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- interrupts mapping:
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 63>;
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interrupt-map = <...>;
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Example of a VE tile description (simplified)
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---------------------------------------------
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/dts-v1/;
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/ {
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model = "V2P-CA5s";
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arm,hbi = <0x225>;
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arm,vexpress,site = <0xf>;
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compatible = "arm,vexpress-v2p-ca5s", "arm,vexpress";
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interrupt-parent = <&gic>;
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#address-cells = <1>;
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#size-cells = <1>;
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chosen { };
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aliases {
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serial0 = &v2m_serial0;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a5";
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reg = <0>;
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};
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};
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gic: interrupt-controller@2c001000 {
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compatible = "arm,cortex-a9-gic";
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#interrupt-cells = <3>;
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#address-cells = <0>;
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interrupt-controller;
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reg = <0x2c001000 0x1000>,
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<0x2c000100 0x100>;
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};
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dcc {
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compatible = "arm,vexpress,config-bus";
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arm,vexpress,config-bridge = <&v2m_sysreg>;
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osc@0 {
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compatible = "arm,vexpress-osc";
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};
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};
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smb {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <1>;
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/* CS0 is visible at 0x08000000 */
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ranges = <0 0 0x08000000 0x04000000>;
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#interrupt-cells = <1>;
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interrupt-map-mask = <0 0 63>;
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/* Active high IRQ 0 is connected to GIC's SPI0 */
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interrupt-map = <0 0 0 &gic 0 0 4>;
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/include/ "vexpress-v2m-rs1.dtsi"
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};
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};
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