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rdma: Remove nes

Browse Source 
This driver was first merged over 10 years ago and has not seen major
activity by the authors in the last 7 years. However, in that time it has
been patched 150 times to adapt it to changing kernel APIs.

Further, the hardware has several issues, like not supporting 64 bit DMA,
that make it rather uninteresting for use with modern systems and RDMA.

Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
Reviewed-by: Leon Romanovsky <leonro@mellanox.com>
Reviewed-by: Shiraz Saleem <shiraz.saleem@intel.com>
Signed-off-by: Doug Ledford <dledford@redhat.com>
This commit is contained in:
Jason Gunthorpe 2019-06-10 16:49:11 -03:00 committed by Doug Ledford
parent cbdc666f3e
commit 2d3c72ed50
19 changed files with 0 additions and 19700 deletions
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17
Documentation/ABI/stable/sysfs-class-infiniband
View File

@ -423,23 +423,6 @@ Description:
(e.g. driver restart on the VM which owns the VF).
sysfs interface for NetEffect RNIC Low-Level iWARP driver (nes)
---------------------------------------------------------------
What: /sys/class/infiniband/nesX/hw_rev
What: /sys/class/infiniband/nesX/hca_type
What: /sys/class/infiniband/nesX/board_id
Date: Feb, 2008
KernelVersion: v2.6.25
Contact: linux-rdma@vger.kernel.org
Description:
hw_rev: (RO) Hardware revision number
hca_type: (RO) Host Channel Adapter type (NEX020)
board_id: (RO) Manufacturing board id
sysfs interface for Chelsio T4/T5 RDMA driver (cxgb4)
-----------------------------------------------------

8
MAINTAINERS
View File

@ -10830,14 +10830,6 @@ F: driver/net/net_failover.c
F: include/net/net_failover.h
F: Documentation/networking/net_failover.rst
NETEFFECT IWARP RNIC DRIVER (IW_NES)
M: Faisal Latif <faisal.latif@intel.com>
L: linux-rdma@vger.kernel.org
W: http://www.intel.com/Products/Server/Adapters/Server-Cluster/Server-Cluster-overview.htm
S: Supported
F: drivers/infiniband/hw/nes/
F: include/uapi/rdma/nes-abi.h
NETEM NETWORK EMULATOR
M: Stephen Hemminger <stephen@networkplumber.org>
L: netem@lists.linux-foundation.org (moderated for non-subscribers)

1
drivers/infiniband/Kconfig
View File

@ -86,7 +86,6 @@ source "drivers/infiniband/hw/efa/Kconfig"
source "drivers/infiniband/hw/i40iw/Kconfig"
source "drivers/infiniband/hw/mlx4/Kconfig"
source "drivers/infiniband/hw/mlx5/Kconfig"
source "drivers/infiniband/hw/nes/Kconfig"
source "drivers/infiniband/hw/ocrdma/Kconfig"
source "drivers/infiniband/hw/vmw_pvrdma/Kconfig"
source "drivers/infiniband/hw/usnic/Kconfig"

1
drivers/infiniband/hw/Makefile
View File

@ -7,7 +7,6 @@ obj-$(CONFIG_INFINIBAND_EFA) += efa/
obj-$(CONFIG_INFINIBAND_I40IW) += i40iw/
obj-$(CONFIG_MLX4_INFINIBAND) += mlx4/
obj-$(CONFIG_MLX5_INFINIBAND) += mlx5/
obj-$(CONFIG_INFINIBAND_NES) += nes/
obj-$(CONFIG_INFINIBAND_OCRDMA) += ocrdma/
obj-$(CONFIG_INFINIBAND_VMWARE_PVRDMA) += vmw_pvrdma/
obj-$(CONFIG_INFINIBAND_USNIC) += usnic/

15
drivers/infiniband/hw/nes/Kconfig
View File

@ -1,15 +0,0 @@
config INFINIBAND_NES
tristate "NetEffect RNIC Driver"
depends on PCI && INET
select LIBCRC32C
---help---
This is the RDMA Network Interface Card (RNIC) driver for
NetEffect Ethernet Cluster Server Adapters.
config INFINIBAND_NES_DEBUG
bool "Verbose debugging output"
depends on INFINIBAND_NES
default n
---help---
This option enables debug messages from the NetEffect RNIC
driver. Select this if you are diagnosing a problem.

3
drivers/infiniband/hw/nes/Makefile
View File

@ -1,3 +0,0 @@
obj-$(CONFIG_INFINIBAND_NES) += iw_nes.o
iw_nes-objs := nes.o nes_hw.o nes_nic.o nes_utils.o nes_verbs.o nes_cm.o nes_mgt.o

1205
drivers/infiniband/hw/nes/nes.c
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File diff suppressed because it is too large Load Diff

574
drivers/infiniband/hw/nes/nes.h
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@ -1,574 +0,0 @@
/*
* Copyright (c) 2006 - 2011 Intel Corporation. All rights reserved.
* Copyright (c) 2005 Open Grid Computing, Inc. All rights reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenIB.org BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef __NES_H
#define __NES_H
#include <linux/netdevice.h>
#include <linux/inetdevice.h>
#include <linux/interrupt.h>
#include <linux/spinlock.h>
#include <linux/kernel.h>
#include <linux/delay.h>
#include <linux/pci.h>
#include <linux/dma-mapping.h>
#include <linux/workqueue.h>
#include <linux/slab.h>
#include <asm/io.h>
#include <linux/crc32c.h>
#include <rdma/ib_smi.h>
#include <rdma/ib_verbs.h>
#include <rdma/ib_pack.h>
#include <rdma/rdma_cm.h>
#include <rdma/iw_cm.h>
#include <rdma/rdma_netlink.h>
#include <rdma/iw_portmap.h>
#define NES_SEND_FIRST_WRITE
#define QUEUE_DISCONNECTS
#define DRV_NAME "iw_nes"
#define DRV_VERSION "1.5.0.1"
#define PFX DRV_NAME ": "
/*
* NetEffect PCI vendor id and NE010 PCI device id.
*/
#ifndef PCI_VENDOR_ID_NETEFFECT /* not in pci.ids yet */
#define PCI_VENDOR_ID_NETEFFECT 0x1678
#define PCI_DEVICE_ID_NETEFFECT_NE020 0x0100
#define PCI_DEVICE_ID_NETEFFECT_NE020_KR 0x0110
#endif
#define NE020_REV 4
#define NE020_REV1 5
#define BAR_0 0
#define BAR_1 2
#define RX_BUF_SIZE (1536 + 8)
#define NES_REG0_SIZE (4 * 1024)
#define NES_TX_TIMEOUT (6*HZ)
#define NES_FIRST_QPN 64
#define NES_SW_CONTEXT_ALIGN 1024
#define NES_MAX_MTU 9000
#define NES_NIC_MAX_NICS 16
#define NES_MAX_ARP_TABLE_SIZE 4096
#define NES_NIC_CEQ_SIZE 8
/* NICs will be on a separate CQ */
#define NES_CCEQ_SIZE ((nesadapter->max_cq / nesadapter->port_count) - 32)
#define NES_MAX_PORT_COUNT 4
#define MAX_DPC_ITERATIONS 128
#define NES_DRV_OPT_ENABLE_MPA_VER_0 0x00000001
#define NES_DRV_OPT_DISABLE_MPA_CRC 0x00000002
#define NES_DRV_OPT_DISABLE_FIRST_WRITE 0x00000004
#define NES_DRV_OPT_DISABLE_INTF 0x00000008
#define NES_DRV_OPT_ENABLE_MSI 0x00000010
#define NES_DRV_OPT_DUAL_LOGICAL_PORT 0x00000020
#define NES_DRV_OPT_SUPRESS_OPTION_BC 0x00000040
#define NES_DRV_OPT_NO_INLINE_DATA 0x00000080
#define NES_DRV_OPT_DISABLE_INT_MOD 0x00000100
#define NES_DRV_OPT_DISABLE_VIRT_WQ 0x00000200
#define NES_DRV_OPT_ENABLE_PAU 0x00000400
#define NES_AEQ_EVENT_TIMEOUT 2500
#define NES_DISCONNECT_EVENT_TIMEOUT 2000
/* debug levels */
/* must match userspace */
#define NES_DBG_HW 0x00000001
#define NES_DBG_INIT 0x00000002
#define NES_DBG_ISR 0x00000004
#define NES_DBG_PHY 0x00000008
#define NES_DBG_NETDEV 0x00000010
#define NES_DBG_CM 0x00000020
#define NES_DBG_CM1 0x00000040
#define NES_DBG_NIC_RX 0x00000080
#define NES_DBG_NIC_TX 0x00000100
#define NES_DBG_CQP 0x00000200
#define NES_DBG_MMAP 0x00000400
#define NES_DBG_MR 0x00000800
#define NES_DBG_PD 0x00001000
#define NES_DBG_CQ 0x00002000
#define NES_DBG_QP 0x00004000
#define NES_DBG_MOD_QP 0x00008000
#define NES_DBG_AEQ 0x00010000
#define NES_DBG_IW_RX 0x00020000
#define NES_DBG_IW_TX 0x00040000
#define NES_DBG_SHUTDOWN 0x00080000
#define NES_DBG_PAU 0x00100000
#define NES_DBG_NLMSG 0x00200000
#define NES_DBG_RSVD1 0x10000000
#define NES_DBG_RSVD2 0x20000000
#define NES_DBG_RSVD3 0x40000000
#define NES_DBG_RSVD4 0x80000000
#define NES_DBG_ALL 0xffffffff
#ifdef CONFIG_INFINIBAND_NES_DEBUG
#define nes_debug(level, fmt, args...) \
do { \
if (level & nes_debug_level) \
printk(KERN_ERR PFX "%s[%u]: " fmt, __func__, __LINE__, ##args); \
} while (0)
#define NES_EVENT_TIMEOUT 1200000
#else
#define nes_debug(level, fmt, args...) no_printk(fmt, ##args)
#define NES_EVENT_TIMEOUT 100000
#endif
#include "nes_hw.h"
#include "nes_verbs.h"
#include "nes_context.h"
#include <rdma/nes-abi.h>
#include "nes_cm.h"
#include "nes_mgt.h"
extern int interrupt_mod_interval;
extern int nes_if_count;
extern int mpa_version;
extern int disable_mpa_crc;
extern unsigned int nes_drv_opt;
extern unsigned int nes_debug_level;
extern unsigned int wqm_quanta;
extern struct list_head nes_adapter_list;
extern atomic_t cm_connects;
extern atomic_t cm_accepts;
extern atomic_t cm_disconnects;
extern atomic_t cm_closes;
extern atomic_t cm_connecteds;
extern atomic_t cm_connect_reqs;
extern atomic_t cm_rejects;
extern atomic_t mod_qp_timouts;
extern atomic_t qps_created;
extern atomic_t qps_destroyed;
extern atomic_t sw_qps_destroyed;
extern u32 mh_detected;
extern u32 mh_pauses_sent;
extern u32 cm_packets_sent;
extern u32 cm_packets_bounced;
extern u32 cm_packets_created;
extern u32 cm_packets_received;
extern u32 cm_packets_dropped;
extern u32 cm_packets_retrans;
extern atomic_t cm_listens_created;
extern atomic_t cm_listens_destroyed;
extern u32 cm_backlog_drops;
extern atomic_t cm_loopbacks;
extern atomic_t cm_nodes_created;
extern atomic_t cm_nodes_destroyed;
extern atomic_t cm_accel_dropped_pkts;
extern atomic_t cm_resets_recvd;
extern atomic_t pau_qps_created;
extern atomic_t pau_qps_destroyed;
extern u32 int_mod_timer_init;
extern u32 int_mod_cq_depth_256;
extern u32 int_mod_cq_depth_128;
extern u32 int_mod_cq_depth_32;
extern u32 int_mod_cq_depth_24;
extern u32 int_mod_cq_depth_16;
extern u32 int_mod_cq_depth_4;
extern u32 int_mod_cq_depth_1;
struct nes_device {
struct nes_adapter *nesadapter;
void __iomem *regs;
void __iomem *index_reg;
struct pci_dev *pcidev;
struct net_device *netdev[NES_NIC_MAX_NICS];
u64 link_status_interrupts;
struct tasklet_struct dpc_tasklet;
spinlock_t indexed_regs_lock;
unsigned long csr_start;
unsigned long doorbell_region;
unsigned long doorbell_start;
unsigned long mac_tx_errors;
unsigned long mac_pause_frames_sent;
unsigned long mac_pause_frames_received;
unsigned long mac_rx_errors;
unsigned long mac_rx_crc_errors;
unsigned long mac_rx_symbol_err_frames;
unsigned long mac_rx_jabber_frames;
unsigned long mac_rx_oversized_frames;
unsigned long mac_rx_short_frames;
unsigned long port_rx_discards;
unsigned long port_tx_discards;
unsigned int mac_index;
unsigned int nes_stack_start;
/* Control Structures */
void *cqp_vbase;
dma_addr_t cqp_pbase;
u32 cqp_mem_size;
u8 ceq_index;
u8 nic_ceq_index;
struct nes_hw_cqp cqp;
struct nes_hw_cq ccq;
struct list_head cqp_avail_reqs;
struct list_head cqp_pending_reqs;
struct nes_cqp_request *nes_cqp_requests;
u32 int_req;
u32 int_stat;
u32 timer_int_req;
u32 timer_only_int_count;
u32 intf_int_req;
u32 last_mac_tx_pauses;
u32 last_used_chunks_tx;
struct list_head list;
u16 base_doorbell_index;
u16 currcq_count;
u16 deepcq_count;
u8 iw_status;
u8 msi_enabled;
u8 netdev_count;
u8 napi_isr_ran;
u8 disable_rx_flow_control;
u8 disable_tx_flow_control;
struct delayed_work work;
u8 link_recheck;
};
/* Receive skb private area - must fit in skb->cb area */
struct nes_rskb_cb {
u64 busaddr;
u32 maplen;
u32 seqnum;
u8 *data_start;
struct nes_qp *nesqp;
};
static inline __le32 get_crc_value(struct nes_v4_quad *nes_quad)
{
u32 crc_value;
crc_value = crc32c(~0, (void *)nes_quad, sizeof (struct nes_v4_quad));
/*
* With commit ef19454b ("[LIB] crc32c: Keep intermediate crc
* state in cpu order"), behavior of crc32c changes on
* big-endian platforms. Our algorithm expects the previous
* behavior; otherwise we have RDMA connection establishment
* issue on big-endian.
*/
return cpu_to_le32(crc_value);
}
static inline void
set_wqe_64bit_value(__le32 *wqe_words, u32 index, u64 value)
{
wqe_words[index] = cpu_to_le32((u32) value);
wqe_words[index + 1] = cpu_to_le32(upper_32_bits(value));
}
static inline void
set_wqe_32bit_value(__le32 *wqe_words, u32 index, u32 value)
{
wqe_words[index] = cpu_to_le32(value);
}
static inline void
nes_fill_init_cqp_wqe(struct nes_hw_cqp_wqe *cqp_wqe, struct nes_device *nesdev)
{
cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_LOW_IDX] = 0;
cqp_wqe->wqe_words[NES_CQP_WQE_COMP_CTX_HIGH_IDX] = 0;
cqp_wqe->wqe_words[NES_CQP_WQE_COMP_SCRATCH_LOW_IDX] = 0;
cqp_wqe->wqe_words[NES_CQP_WQE_COMP_SCRATCH_HIGH_IDX] = 0;
cqp_wqe->wqe_words[NES_CQP_STAG_WQE_PBL_BLK_COUNT_IDX] = 0;
cqp_wqe->wqe_words[NES_CQP_STAG_WQE_PBL_LEN_IDX] = 0;
cqp_wqe->wqe_words[NES_CQP_STAG_WQE_LEN_LOW_IDX] = 0;
cqp_wqe->wqe_words[NES_CQP_STAG_WQE_PA_LOW_IDX] = 0;
cqp_wqe->wqe_words[NES_CQP_STAG_WQE_PA_HIGH_IDX] = 0;
}
static inline void
nes_fill_init_qp_wqe(struct nes_hw_qp_wqe *wqe, struct nes_qp *nesqp, u32 head)
{
u32 value;
value = ((u32)((unsigned long) nesqp)) | head;
set_wqe_32bit_value(wqe->wqe_words, NES_IWARP_SQ_WQE_COMP_CTX_HIGH_IDX,
(u32)(upper_32_bits((unsigned long)(nesqp))));
set_wqe_32bit_value(wqe->wqe_words, NES_IWARP_SQ_WQE_COMP_CTX_LOW_IDX, value);
}
/* Read from memory-mapped device */
static inline u32 nes_read_indexed(struct nes_device *nesdev, u32 reg_index)
{
unsigned long flags;
void __iomem *addr = nesdev->index_reg;
u32 value;
spin_lock_irqsave(&nesdev->indexed_regs_lock, flags);
writel(reg_index, addr);
value = readl((void __iomem *)addr + 4);
spin_unlock_irqrestore(&nesdev->indexed_regs_lock, flags);
return value;
}
static inline u32 nes_read32(const void __iomem *addr)
{
return readl(addr);
}
static inline u16 nes_read16(const void __iomem *addr)
{
return readw(addr);
}
static inline u8 nes_read8(const void __iomem *addr)
{
return readb(addr);
}
/* Write to memory-mapped device */
static inline void nes_write_indexed(struct nes_device *nesdev, u32 reg_index, u32 val)
{
unsigned long flags;
void __iomem *addr = nesdev->index_reg;
spin_lock_irqsave(&nesdev->indexed_regs_lock, flags);
writel(reg_index, addr);
writel(val, (void __iomem *)addr + 4);
spin_unlock_irqrestore(&nesdev->indexed_regs_lock, flags);
}
static inline void nes_write32(void __iomem *addr, u32 val)
{
writel(val, addr);
}
static inline void nes_write16(void __iomem *addr, u16 val)
{
writew(val, addr);
}
static inline void nes_write8(void __iomem *addr, u8 val)
{
writeb(val, addr);
}
enum nes_resource {
NES_RESOURCE_MW = 1,
NES_RESOURCE_FAST_MR,
NES_RESOURCE_PHYS_MR,
NES_RESOURCE_USER_MR,
NES_RESOURCE_PD,
NES_RESOURCE_QP,
NES_RESOURCE_CQ,
NES_RESOURCE_ARP
};
static inline int nes_alloc_resource(struct nes_adapter *nesadapter,
unsigned long *resource_array, u32 max_resources,
u32 *req_resource_num, u32 *next, enum nes_resource resource_type)
{
unsigned long flags;
u32 resource_num;
spin_lock_irqsave(&nesadapter->resource_lock, flags);
resource_num = find_next_zero_bit(resource_array, max_resources, *next);
if (resource_num >= max_resources) {
resource_num = find_first_zero_bit(resource_array, max_resources);
if (resource_num >= max_resources) {
printk(KERN_ERR PFX "%s: No available resources [type=%u].\n", __func__, resource_type);
spin_unlock_irqrestore(&nesadapter->resource_lock, flags);
return -EMFILE;
}
}
set_bit(resource_num, resource_array);
*next = resource_num+1;
if (*next == max_resources) {
*next = 0;
}
spin_unlock_irqrestore(&nesadapter->resource_lock, flags);
*req_resource_num = resource_num;
return 0;
}
static inline int nes_is_resource_allocated(struct nes_adapter *nesadapter,
unsigned long *resource_array, u32 resource_num)
{
unsigned long flags;
int bit_is_set;
spin_lock_irqsave(&nesadapter->resource_lock, flags);
bit_is_set = test_bit(resource_num, resource_array);
nes_debug(NES_DBG_HW, "resource_num %u is%s allocated.\n",
resource_num, (bit_is_set ? "": " not"));
spin_unlock_irqrestore(&nesadapter->resource_lock, flags);
return bit_is_set;
}
static inline void nes_free_resource(struct nes_adapter *nesadapter,
unsigned long *resource_array, u32 resource_num)
{
unsigned long flags;
spin_lock_irqsave(&nesadapter->resource_lock, flags);
clear_bit(resource_num, resource_array);
spin_unlock_irqrestore(&nesadapter->resource_lock, flags);
}
static inline struct nes_vnic *to_nesvnic(struct ib_device *ibdev)
{
return container_of(ibdev, struct nes_ib_device, ibdev)->nesvnic;
}
static inline struct nes_pd *to_nespd(struct ib_pd *ibpd)
{
return container_of(ibpd, struct nes_pd, ibpd);
}
static inline struct nes_ucontext *to_nesucontext(struct ib_ucontext *ibucontext)
{
return container_of(ibucontext, struct nes_ucontext, ibucontext);
}
static inline struct nes_mr *to_nesmr(struct ib_mr *ibmr)
{
return container_of(ibmr, struct nes_mr, ibmr);
}
static inline struct nes_mr *to_nesmr_from_ibfmr(struct ib_fmr *ibfmr)
{
return container_of(ibfmr, struct nes_mr, ibfmr);
}
static inline struct nes_mr *to_nesmw(struct ib_mw *ibmw)
{
return container_of(ibmw, struct nes_mr, ibmw);
}
static inline struct nes_fmr *to_nesfmr(struct nes_mr *nesmr)
{
return container_of(nesmr, struct nes_fmr, nesmr);
}
static inline struct nes_cq *to_nescq(struct ib_cq *ibcq)
{
return container_of(ibcq, struct nes_cq, ibcq);
}
static inline struct nes_qp *to_nesqp(struct ib_qp *ibqp)
{
return container_of(ibqp, struct nes_qp, ibqp);
}
/* nes.c */
void nes_add_ref(struct ib_qp *);
void nes_rem_ref(struct ib_qp *);
struct ib_qp *nes_get_qp(struct ib_device *, int);
/* nes_hw.c */
struct nes_adapter *nes_init_adapter(struct nes_device *, u8);
void nes_nic_init_timer_defaults(struct nes_device *, u8);
void nes_destroy_adapter(struct nes_adapter *);
int nes_init_cqp(struct nes_device *);
int nes_init_phy(struct nes_device *);
int nes_init_nic_qp(struct nes_device *, struct net_device *);
void nes_destroy_nic_qp(struct nes_vnic *);
int nes_napi_isr(struct nes_device *);
void nes_dpc(unsigned long);
void nes_nic_ce_handler(struct nes_device *, struct nes_hw_nic_cq *);
void nes_iwarp_ce_handler(struct nes_device *, struct nes_hw_cq *);
int nes_destroy_cqp(struct nes_device *);
int nes_nic_cm_xmit(struct sk_buff *, struct net_device *);
void nes_recheck_link_status(struct work_struct *work);
void nes_terminate_timeout(struct timer_list *t);
/* nes_nic.c */
struct net_device *nes_netdev_init(struct nes_device *, void __iomem *);
void nes_netdev_destroy(struct net_device *);
int nes_nic_cm_xmit(struct sk_buff *, struct net_device *);
/* nes_cm.c */
void *nes_cm_create(struct net_device *);
int nes_cm_recv(struct sk_buff *, struct net_device *);
void nes_update_arp(unsigned char *, u32, u32, u16, u16);
void nes_manage_arp_cache(struct net_device *, unsigned char *, u32, u32);
void nes_sock_release(struct nes_qp *, unsigned long *);
void flush_wqes(struct nes_device *nesdev, struct nes_qp *, u32, u32);
int nes_manage_apbvt(struct nes_vnic *, u32, u32, u32);
int nes_cm_disconn(struct nes_qp *);
void nes_cm_disconn_worker(void *);
/* nes_verbs.c */
int nes_hw_modify_qp(struct nes_device *, struct nes_qp *, u32, u32, u32);
int nes_modify_qp(struct ib_qp *, struct ib_qp_attr *, int, struct ib_udata *);
struct nes_ib_device *nes_init_ofa_device(struct net_device *);
void nes_port_ibevent(struct nes_vnic *nesvnic);
void nes_destroy_ofa_device(struct nes_ib_device *);
int nes_register_ofa_device(struct nes_ib_device *);
/* nes_util.c */
int nes_read_eeprom_values(struct nes_device *, struct nes_adapter *);
void nes_write_1G_phy_reg(struct nes_device *, u8, u8, u16);
void nes_read_1G_phy_reg(struct nes_device *, u8, u8, u16 *);
void nes_write_10G_phy_reg(struct nes_device *, u16, u8, u16, u16);
void nes_read_10G_phy_reg(struct nes_device *, u8, u8, u16);
struct nes_cqp_request *nes_get_cqp_request(struct nes_device *);
void nes_free_cqp_request(struct nes_device *nesdev,
struct nes_cqp_request *cqp_request);
void nes_put_cqp_request(struct nes_device *nesdev,
struct nes_cqp_request *cqp_request);
void nes_post_cqp_request(struct nes_device *, struct nes_cqp_request *);
int nes_arp_table(struct nes_device *, u32, u8 *, u32);
void nes_mh_fix(struct timer_list *t);
void nes_clc(struct timer_list *t);
void nes_dump_mem(unsigned int, void *, int);
u32 nes_crc32(u32, u32, u32, u32, u8 *, u32, u32, u32);
#endif /* __NES_H */

3992
drivers/infiniband/hw/nes/nes_cm.c
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drivers/infiniband/hw/nes/nes_cm.h
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/*
* Copyright (c) 2006 - 2014 Intel Corporation. All rights reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenIB.org BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
*/
#ifndef NES_CM_H
#define NES_CM_H
#define QUEUE_EVENTS
#define NES_MANAGE_APBVT_DEL 0
#define NES_MANAGE_APBVT_ADD 1
#define NES_MPA_REQUEST_ACCEPT 1
#define NES_MPA_REQUEST_REJECT 2
/* IETF MPA -- defines, enums, structs */
#define IEFT_MPA_KEY_REQ "MPA ID Req Frame"
#define IEFT_MPA_KEY_REP "MPA ID Rep Frame"
#define IETF_MPA_KEY_SIZE 16
#define IETF_MPA_VERSION 1
#define IETF_MAX_PRIV_DATA_LEN 512
#define IETF_MPA_FRAME_SIZE 20
#define IETF_RTR_MSG_SIZE 4
#define IETF_MPA_V2_FLAG 0x10
/* IETF RTR MSG Fields */
#define IETF_PEER_TO_PEER 0x8000
#define IETF_FLPDU_ZERO_LEN 0x4000
#define IETF_RDMA0_WRITE 0x8000
#define IETF_RDMA0_READ 0x4000
#define IETF_NO_IRD_ORD 0x3FFF
#define NES_MAX_IRD 0x40
#define NES_MAX_ORD 0x7F
enum ietf_mpa_flags {
IETF_MPA_FLAGS_MARKERS = 0x80, /* receive Markers */
IETF_MPA_FLAGS_CRC = 0x40, /* receive Markers */
IETF_MPA_FLAGS_REJECT = 0x20, /* Reject */
};
struct ietf_mpa_v1 {
u8 key[IETF_MPA_KEY_SIZE];
u8 flags;
u8 rev;
__be16 priv_data_len;
u8 priv_data[0];
};
#define ietf_mpa_req_resp_frame ietf_mpa_frame
struct ietf_rtr_msg {
__be16 ctrl_ird;
__be16 ctrl_ord;
};
struct ietf_mpa_v2 {
u8 key[IETF_MPA_KEY_SIZE];
u8 flags;
u8 rev;
__be16 priv_data_len;
struct ietf_rtr_msg rtr_msg;
u8 priv_data[0];
};
struct nes_v4_quad {
u32 rsvd0;
__le32 DstIpAdrIndex; /* Only most significant 5 bits are valid */
__be32 SrcIpadr;
__be16 TcpPorts[2]; /* src is low, dest is high */
};
struct nes_cm_node;
enum nes_timer_type {
NES_TIMER_TYPE_SEND,
NES_TIMER_TYPE_RECV,
NES_TIMER_NODE_CLEANUP,
NES_TIMER_TYPE_CLOSE,
};
#define NES_PASSIVE_STATE_INDICATED 0
#define NES_DO_NOT_SEND_RESET_EVENT 1
#define NES_SEND_RESET_EVENT 2
#define MAX_NES_IFS 4
#define SET_ACK 1
#define SET_SYN 2
#define SET_FIN 4
#define SET_RST 8
#define TCP_OPTIONS_PADDING 3
struct option_base {
u8 optionnum;
u8 length;
};
enum option_numbers {
OPTION_NUMBER_END,
OPTION_NUMBER_NONE,
OPTION_NUMBER_MSS,
OPTION_NUMBER_WINDOW_SCALE,
OPTION_NUMBER_SACK_PERM,
OPTION_NUMBER_SACK,
OPTION_NUMBER_WRITE0 = 0xbc
};
struct option_mss {
u8 optionnum;
u8 length;
__be16 mss;
};
struct option_windowscale {
u8 optionnum;
u8 length;
u8 shiftcount;
};
union all_known_options {
char as_end;
struct option_base as_base;
struct option_mss as_mss;
struct option_windowscale as_windowscale;
};
struct nes_timer_entry {
struct list_head list;
unsigned long timetosend; /* jiffies */
struct sk_buff *skb;
u32 type;
u32 retrycount;
u32 retranscount;
u32 context;
u32 seq_num;
u32 send_retrans;
int close_when_complete;
struct net_device *netdev;
};
#define NES_DEFAULT_RETRYS 64
#define NES_DEFAULT_RETRANS 8
#ifdef CONFIG_INFINIBAND_NES_DEBUG
#define NES_RETRY_TIMEOUT (1000*HZ/1000)
#else
#define NES_RETRY_TIMEOUT (3000*HZ/1000)
#endif
#define NES_SHORT_TIME (10)
#define NES_LONG_TIME (2000*HZ/1000)
#define NES_MAX_TIMEOUT ((unsigned long) (12*HZ))
#define NES_CM_HASHTABLE_SIZE 1024
#define NES_CM_TCP_TIMER_INTERVAL 3000
#define NES_CM_DEFAULT_MTU 1540
#define NES_CM_DEFAULT_FRAME_CNT 10
#define NES_CM_THREAD_STACK_SIZE 256
#define NES_CM_DEFAULT_RCV_WND 64240 // before we know that window scaling is allowed
#define NES_CM_DEFAULT_RCV_WND_SCALED 256960 // after we know that window scaling is allowed
#define NES_CM_DEFAULT_RCV_WND_SCALE 2
#define NES_CM_DEFAULT_FREE_PKTS 0x000A
#define NES_CM_FREE_PKT_LO_WATERMARK 2
#define NES_CM_DEFAULT_MSS 536
#define NES_CM_DEF_SEQ 0x159bf75f
#define NES_CM_DEF_LOCAL_ID 0x3b47
#define NES_CM_DEF_SEQ2 0x18ed5740
#define NES_CM_DEF_LOCAL_ID2 0xb807
#define MAX_CM_BUFFER (IETF_MPA_FRAME_SIZE + IETF_RTR_MSG_SIZE + IETF_MAX_PRIV_DATA_LEN)
typedef u32 nes_addr_t;
#define nes_cm_tsa_context nes_qp_context
struct nes_qp;
/* cm node transition states */
enum nes_cm_node_state {
NES_CM_STATE_UNKNOWN,
NES_CM_STATE_INITED,
NES_CM_STATE_LISTENING,
NES_CM_STATE_SYN_RCVD,
NES_CM_STATE_SYN_SENT,
NES_CM_STATE_ONE_SIDE_ESTABLISHED,
NES_CM_STATE_ESTABLISHED,
NES_CM_STATE_ACCEPTING,
NES_CM_STATE_MPAREQ_SENT,
NES_CM_STATE_MPAREQ_RCVD,
NES_CM_STATE_MPAREJ_RCVD,
NES_CM_STATE_TSA,
NES_CM_STATE_FIN_WAIT1,
NES_CM_STATE_FIN_WAIT2,
NES_CM_STATE_CLOSE_WAIT,
NES_CM_STATE_TIME_WAIT,
NES_CM_STATE_LAST_ACK,
NES_CM_STATE_CLOSING,
NES_CM_STATE_LISTENER_DESTROYED,
NES_CM_STATE_CLOSED
};
enum mpa_frame_version {
IETF_MPA_V1 = 1,
IETF_MPA_V2 = 2
};
enum mpa_frame_key {
MPA_KEY_REQUEST,
MPA_KEY_REPLY
};
enum send_rdma0 {
SEND_RDMA_READ_ZERO = 1,
SEND_RDMA_WRITE_ZERO = 2
};
enum nes_tcpip_pkt_type {
NES_PKT_TYPE_UNKNOWN,
NES_PKT_TYPE_SYN,
NES_PKT_TYPE_SYNACK,
NES_PKT_TYPE_ACK,
NES_PKT_TYPE_FIN,
NES_PKT_TYPE_RST
};
/* type of nes connection */
enum nes_cm_conn_type {
NES_CM_IWARP_CONN_TYPE,
};
/* CM context params */
struct nes_cm_tcp_context {
u8 client;
u32 loc_seq_num;
u32 loc_ack_num;
u32 rem_ack_num;
u32 rcv_nxt;
u32 loc_id;
u32 rem_id;
u32 snd_wnd;
u32 max_snd_wnd;
u32 rcv_wnd;
u32 mss;
u8 snd_wscale;
u8 rcv_wscale;
struct nes_cm_tsa_context tsa_cntxt;
};
enum nes_cm_listener_state {
NES_CM_LISTENER_PASSIVE_STATE = 1,
NES_CM_LISTENER_ACTIVE_STATE = 2,
NES_CM_LISTENER_EITHER_STATE = 3
};
struct nes_cm_listener {
struct list_head list;
struct nes_cm_core *cm_core;
u8 loc_mac[ETH_ALEN];
nes_addr_t loc_addr;
u16 loc_port;
struct iw_cm_id *cm_id;
enum nes_cm_conn_type conn_type;
atomic_t ref_count;
struct nes_vnic *nesvnic;
atomic_t pend_accepts_cnt;
int backlog;
enum nes_cm_listener_state listener_state;
u32 reused_node;
u8 tos;
};
/* per connection node and node state information */
struct nes_cm_node {
nes_addr_t loc_addr, rem_addr;
u16 loc_port, rem_port;
u8 loc_mac[ETH_ALEN];
u8 rem_mac[ETH_ALEN];
enum nes_cm_node_state state;
struct nes_cm_tcp_context tcp_cntxt;
struct nes_cm_core *cm_core;
struct sk_buff_head resend_list;
atomic_t ref_count;
struct net_device *netdev;
struct nes_cm_node *loopbackpartner;
struct nes_timer_entry *send_entry;
struct nes_timer_entry *recv_entry;
spinlock_t retrans_list_lock;
enum send_rdma0 send_rdma0_op;
union {
struct ietf_mpa_v1 mpa_frame;
struct ietf_mpa_v2 mpa_v2_frame;
u8 mpa_frame_buf[MAX_CM_BUFFER];
};
enum mpa_frame_version mpa_frame_rev;
u16 ird_size;
u16 ord_size;
u16 mpav2_ird_ord;
u16 mpa_frame_size;
struct iw_cm_id *cm_id;
struct list_head list;
bool accelerated;
struct nes_cm_listener *listener;
enum nes_cm_conn_type conn_type;
struct nes_vnic *nesvnic;
int apbvt_set;
int accept_pend;
struct list_head timer_entry;
struct list_head reset_entry;
struct nes_qp *nesqp;
atomic_t passive_state;
u8 tos;
};
/* structure for client or CM to fill when making CM api calls. */
/* - only need to set relevant data, based on op. */
struct nes_cm_info {
union {
struct iw_cm_id *cm_id;
struct net_device *netdev;
};
u16 loc_port;
u16 rem_port;
nes_addr_t loc_addr;
nes_addr_t rem_addr;
enum nes_cm_conn_type conn_type;
int backlog;
};
/* CM event codes */
enum nes_cm_event_type {
NES_CM_EVENT_UNKNOWN,
NES_CM_EVENT_ESTABLISHED,
NES_CM_EVENT_MPA_REQ,
NES_CM_EVENT_MPA_CONNECT,
NES_CM_EVENT_MPA_ACCEPT,
NES_CM_EVENT_MPA_REJECT,
NES_CM_EVENT_MPA_ESTABLISHED,
NES_CM_EVENT_CONNECTED,
NES_CM_EVENT_CLOSED,
NES_CM_EVENT_RESET,
NES_CM_EVENT_DROPPED_PKT,
NES_CM_EVENT_CLOSE_IMMED,
NES_CM_EVENT_CLOSE_HARD,
NES_CM_EVENT_CLOSE_CLEAN,
NES_CM_EVENT_ABORTED,
NES_CM_EVENT_SEND_FIRST
};
/* event to post to CM event handler */
struct nes_cm_event {
enum nes_cm_event_type type;
struct nes_cm_info cm_info;
struct work_struct event_work;
struct nes_cm_node *cm_node;
};
struct nes_cm_core {
enum nes_cm_node_state state;
atomic_t listen_node_cnt;
struct nes_cm_node listen_list;
spinlock_t listen_list_lock;
u32 mtu;
u32 free_tx_pkt_max;
u32 rx_pkt_posted;
atomic_t ht_node_cnt;
struct list_head connected_nodes;
/* struct list_head hashtable[NES_CM_HASHTABLE_SIZE]; */
spinlock_t ht_lock;
struct timer_list tcp_timer;
const struct nes_cm_ops *api;
int (*post_event)(struct nes_cm_event *event);
atomic_t events_posted;
struct workqueue_struct *event_wq;
struct workqueue_struct *disconn_wq;
atomic_t node_cnt;
u64 aborted_connects;
u32 options;
struct nes_cm_node *current_listen_node;
};
#define NES_CM_SET_PKT_SIZE (1 << 1)
#define NES_CM_SET_FREE_PKT_Q_SIZE (1 << 2)
/* CM ops/API for client interface */
struct nes_cm_ops {
int (*accelerated)(struct nes_cm_core *, struct nes_cm_node *);
struct nes_cm_listener * (*listen)(struct nes_cm_core *, struct nes_vnic *,
struct nes_cm_info *);
int (*stop_listener)(struct nes_cm_core *, struct nes_cm_listener *);
struct nes_cm_node * (*connect)(struct nes_cm_core *,
struct nes_vnic *, u16, void *,
struct nes_cm_info *);
int (*close)(struct nes_cm_core *, struct nes_cm_node *);
int (*accept)(struct nes_cm_core *, struct nes_cm_node *);
int (*reject)(struct nes_cm_core *, struct nes_cm_node *);
int (*recv_pkt)(struct nes_cm_core *, struct nes_vnic *,
struct sk_buff *);
int (*destroy_cm_core)(struct nes_cm_core *);
int (*get)(struct nes_cm_core *);
int (*set)(struct nes_cm_core *, u32, u32);
};
int schedule_nes_timer(struct nes_cm_node *, struct sk_buff *,
enum nes_timer_type, int, int);
int nes_accept(struct iw_cm_id *, struct iw_cm_conn_param *);
int nes_reject(struct iw_cm_id *, const void *, u8);
int nes_connect(struct iw_cm_id *, struct iw_cm_conn_param *);
int nes_create_listen(struct iw_cm_id *, int);
int nes_destroy_listen(struct iw_cm_id *);
int nes_cm_recv(struct sk_buff *, struct net_device *);
int nes_cm_start(void);
int nes_cm_stop(void);
int nes_add_ref_cm_node(struct nes_cm_node *cm_node);
int nes_rem_ref_cm_node(struct nes_cm_node *cm_node);
#endif /* NES_CM_H */

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drivers/infiniband/hw/nes/nes_context.h
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/*
* Copyright (c) 2006 - 2011 Intel Corporation. All rights reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenIB.org BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef NES_CONTEXT_H
#define NES_CONTEXT_H
struct nes_qp_context {
__le32 misc;
__le32 cqs;
__le32 sq_addr_low;
__le32 sq_addr_high;
__le32 rq_addr_low;
__le32 rq_addr_high;
__le32 misc2;
__le16 tcpPorts[2];
__le32 ip0;
__le32 ip1;
__le32 ip2;
__le32 ip3;
__le32 mss;
__le32 arp_index_vlan;
__le32 tcp_state_flow_label;
__le32 pd_index_wscale;
__le32 keepalive;
u32 ts_recent;
u32 ts_age;
__le32 snd_nxt;
__le32 snd_wnd;
__le32 rcv_nxt;
__le32 rcv_wnd;
__le32 snd_max;
__le32 snd_una;
u32 srtt;
__le32 rttvar;
__le32 ssthresh;
__le32 cwnd;
__le32 snd_wl1;
__le32 snd_wl2;
__le32 max_snd_wnd;
__le32 ts_val_delta;
u32 retransmit;
u32 probe_cnt;
u32 hte_index;
__le32 q2_addr_low;
__le32 q2_addr_high;
__le32 ird_index;
u32 Rsvd3;
__le32 ird_ord_sizes;
u32 mrkr_offset;
__le32 aeq_token_low;
__le32 aeq_token_high;
};
/* QP Context Misc Field */
#define NES_QPCONTEXT_MISC_IWARP_VER_MASK 0x00000003
#define NES_QPCONTEXT_MISC_IWARP_VER_SHIFT 0
#define NES_QPCONTEXT_MISC_EFB_SIZE_MASK 0x000000C0
#define NES_QPCONTEXT_MISC_EFB_SIZE_SHIFT 6
#define NES_QPCONTEXT_MISC_RQ_SIZE_MASK 0x00000300
#define NES_QPCONTEXT_MISC_RQ_SIZE_SHIFT 8
#define NES_QPCONTEXT_MISC_SQ_SIZE_MASK 0x00000c00
#define NES_QPCONTEXT_MISC_SQ_SIZE_SHIFT 10
#define NES_QPCONTEXT_MISC_PCI_FCN_MASK 0x00007000
#define NES_QPCONTEXT_MISC_PCI_FCN_SHIFT 12
#define NES_QPCONTEXT_MISC_DUP_ACKS_MASK 0x00070000
#define NES_QPCONTEXT_MISC_DUP_ACKS_SHIFT 16
enum nes_qp_context_misc_bits {
NES_QPCONTEXT_MISC_RX_WQE_SIZE = 0x00000004,
NES_QPCONTEXT_MISC_IPV4 = 0x00000008,
NES_QPCONTEXT_MISC_DO_NOT_FRAG = 0x00000010,
NES_QPCONTEXT_MISC_INSERT_VLAN = 0x00000020,
NES_QPCONTEXT_MISC_DROS = 0x00008000,
NES_QPCONTEXT_MISC_WSCALE = 0x00080000,
NES_QPCONTEXT_MISC_KEEPALIVE = 0x00100000,
NES_QPCONTEXT_MISC_TIMESTAMP = 0x00200000,
NES_QPCONTEXT_MISC_SACK = 0x00400000,
NES_QPCONTEXT_MISC_RDMA_WRITE_EN = 0x00800000,
NES_QPCONTEXT_MISC_RDMA_READ_EN = 0x01000000,
NES_QPCONTEXT_MISC_WBIND_EN = 0x10000000,
NES_QPCONTEXT_MISC_FAST_REGISTER_EN = 0x20000000,
NES_QPCONTEXT_MISC_PRIV_EN = 0x40000000,
NES_QPCONTEXT_MISC_NO_NAGLE = 0x80000000
};
enum nes_qp_acc_wq_sizes {
HCONTEXT_TSA_WQ_SIZE_4 = 0,
HCONTEXT_TSA_WQ_SIZE_32 = 1,
HCONTEXT_TSA_WQ_SIZE_128 = 2,
HCONTEXT_TSA_WQ_SIZE_512 = 3
};
/* QP Context Misc2 Fields */
#define NES_QPCONTEXT_MISC2_TTL_MASK 0x000000ff
#define NES_QPCONTEXT_MISC2_TTL_SHIFT 0
#define NES_QPCONTEXT_MISC2_HOP_LIMIT_MASK 0x000000ff
#define NES_QPCONTEXT_MISC2_HOP_LIMIT_SHIFT 0
#define NES_QPCONTEXT_MISC2_LIMIT_MASK 0x00000300
#define NES_QPCONTEXT_MISC2_LIMIT_SHIFT 8
#define NES_QPCONTEXT_MISC2_NIC_INDEX_MASK 0x0000fc00
#define NES_QPCONTEXT_MISC2_NIC_INDEX_SHIFT 10
#define NES_QPCONTEXT_MISC2_SRC_IP_MASK 0x001f0000
#define NES_QPCONTEXT_MISC2_SRC_IP_SHIFT 16
#define NES_QPCONTEXT_MISC2_TOS_MASK 0xff000000
#define NES_QPCONTEXT_MISC2_TOS_SHIFT 24
#define NES_QPCONTEXT_MISC2_TRAFFIC_CLASS_MASK 0xff000000
#define NES_QPCONTEXT_MISC2_TRAFFIC_CLASS_SHIFT 24
/* QP Context Tcp State/Flow Label Fields */
#define NES_QPCONTEXT_TCPFLOW_FLOW_LABEL_MASK 0x000fffff
#define NES_QPCONTEXT_TCPFLOW_FLOW_LABEL_SHIFT 0
#define NES_QPCONTEXT_TCPFLOW_TCP_STATE_MASK 0xf0000000
#define NES_QPCONTEXT_TCPFLOW_TCP_STATE_SHIFT 28
enum nes_qp_tcp_state {
NES_QPCONTEXT_TCPSTATE_CLOSED = 1,
NES_QPCONTEXT_TCPSTATE_EST = 5,
NES_QPCONTEXT_TCPSTATE_TIME_WAIT = 11,
};
/* QP Context PD Index/wscale Fields */
#define NES_QPCONTEXT_PDWSCALE_RCV_WSCALE_MASK 0x0000000f
#define NES_QPCONTEXT_PDWSCALE_RCV_WSCALE_SHIFT 0
#define NES_QPCONTEXT_PDWSCALE_SND_WSCALE_MASK 0x00000f00
#define NES_QPCONTEXT_PDWSCALE_SND_WSCALE_SHIFT 8
#define NES_QPCONTEXT_PDWSCALE_PDINDEX_MASK 0xffff0000
#define NES_QPCONTEXT_PDWSCALE_PDINDEX_SHIFT 16
/* QP Context Keepalive Fields */
#define NES_QPCONTEXT_KEEPALIVE_DELTA_MASK 0x0000ffff
#define NES_QPCONTEXT_KEEPALIVE_DELTA_SHIFT 0
#define NES_QPCONTEXT_KEEPALIVE_PROBE_CNT_MASK 0x00ff0000
#define NES_QPCONTEXT_KEEPALIVE_PROBE_CNT_SHIFT 16
#define NES_QPCONTEXT_KEEPALIVE_INTV_MASK 0xff000000
#define NES_QPCONTEXT_KEEPALIVE_INTV_SHIFT 24
/* QP Context ORD/IRD Fields */
#define NES_QPCONTEXT_ORDIRD_ORDSIZE_MASK 0x0000007f
#define NES_QPCONTEXT_ORDIRD_ORDSIZE_SHIFT 0
#define NES_QPCONTEXT_ORDIRD_IRDSIZE_MASK 0x00030000
#define NES_QPCONTEXT_ORDIRD_IRDSIZE_SHIFT 16
#define NES_QPCONTEXT_ORDIRD_IWARP_MODE_MASK 0x30000000
#define NES_QPCONTEXT_ORDIRD_IWARP_MODE_SHIFT 28
enum nes_ord_ird_bits {
NES_QPCONTEXT_ORDIRD_WRPDU = 0x02000000,
NES_QPCONTEXT_ORDIRD_LSMM_PRESENT = 0x04000000,
NES_QPCONTEXT_ORDIRD_ALSMM = 0x08000000,
NES_QPCONTEXT_ORDIRD_AAH = 0x40000000,
NES_QPCONTEXT_ORDIRD_RNMC = 0x80000000
};
enum nes_iwarp_qp_state {
NES_QPCONTEXT_IWARP_STATE_NONEXIST = 0,
NES_QPCONTEXT_IWARP_STATE_IDLE = 1,
NES_QPCONTEXT_IWARP_STATE_RTS = 2,
NES_QPCONTEXT_IWARP_STATE_CLOSING = 3,
NES_QPCONTEXT_IWARP_STATE_TERMINATE = 5,
NES_QPCONTEXT_IWARP_STATE_ERROR = 6
};
#endif /* NES_CONTEXT_H */

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drivers/infiniband/hw/nes/nes_hw.c
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1380
drivers/infiniband/hw/nes/nes_hw.h
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1155
drivers/infiniband/hw/nes/nes_mgt.c
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drivers/infiniband/hw/nes/nes_mgt.h
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@ -1,97 +0,0 @@
/*
* Copyright (c) 2006 - 2011 Intel-NE, Inc. All rights reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenIB.org BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#ifndef __NES_MGT_H
#define __NES_MGT_H
#define MPA_FRAMING 6 /* length is 2 bytes, crc is 4 bytes */
int nes_init_mgt_qp(struct nes_device *nesdev, struct net_device *netdev, struct nes_vnic *nesvnic);
void nes_queue_mgt_skbs(struct sk_buff *skb, struct nes_vnic *nesvnic, struct nes_qp *nesqp);
void nes_destroy_mgt(struct nes_vnic *nesvnic);
void nes_destroy_pau_qp(struct nes_device *nesdev, struct nes_qp *nesqp);
struct nes_hw_mgt {
struct nes_hw_nic_rq_wqe *rq_vbase; /* virtual address of rq */
dma_addr_t rq_pbase; /* PCI memory for host rings */
struct sk_buff *rx_skb[NES_NIC_WQ_SIZE];
u16 qp_id;
u16 sq_head;
u16 rq_head;
u16 rq_tail;
u16 rq_size;
u8 replenishing_rq;
u8 reserved;
spinlock_t rq_lock;
};
struct nes_vnic_mgt {
struct nes_vnic *nesvnic;
struct nes_hw_mgt mgt;
struct nes_hw_nic_cq mgt_cq;
atomic_t rx_skbs_needed;
struct timer_list rq_wqes_timer;
atomic_t rx_skb_timer_running;
};
#define MAX_FPDU_FRAGS 4
struct pau_fpdu_frag {
struct sk_buff *skb;
u64 physaddr;
u32 frag_len;
bool cmplt;
};
struct pau_fpdu_info {
struct nes_qp *nesqp;
struct nes_cqp_request *cqp_request;
void *hdr_vbase;
dma_addr_t hdr_pbase;
int hdr_len;
u16 data_len;
u16 frag_cnt;
struct pau_fpdu_frag frags[MAX_FPDU_FRAGS];
};
enum pau_qh_state {
PAU_DEL_QH,
PAU_ADD_LB_QH,
PAU_READY
};
struct pau_qh_chg {
struct nes_device *nesdev;
struct nes_vnic *nesvnic;
struct nes_qp *nesqp;
};
#endif /* __NES_MGT_H */

1870
drivers/infiniband/hw/nes/nes_nic.c
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drivers/infiniband/hw/nes/nes_utils.c
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/*
* Copyright (c) 2006 - 2011 Intel Corporation. All rights reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenIB.org BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
*/
#include <linux/module.h>
#include <linux/moduleparam.h>
#include <linux/netdevice.h>
#include <linux/etherdevice.h>
#include <linux/ethtool.h>
#include <linux/mii.h>
#include <linux/if_vlan.h>
#include <linux/slab.h>
#include <linux/crc32.h>
#include <linux/in.h>
#include <linux/ip.h>
#include <linux/tcp.h>
#include <linux/init.h>
#include <linux/kernel.h>
#include <asm/io.h>
#include <asm/irq.h>
#include <asm/byteorder.h>
#include "nes.h"
static u16 nes_read16_eeprom(void __iomem *addr, u16 offset);
u32 mh_detected;
u32 mh_pauses_sent;
static u32 nes_set_pau(struct nes_device *nesdev)
{
u32 ret = 0;
u32 counter;
nes_write_indexed(nesdev, NES_IDX_GPR2, NES_ENABLE_PAU);
nes_write_indexed(nesdev, NES_IDX_GPR_TRIGGER, 1);
for (counter = 0; counter < NES_PAU_COUNTER; counter++) {
udelay(30);
if (!nes_read_indexed(nesdev, NES_IDX_GPR2)) {
printk(KERN_INFO PFX "PAU is supported.\n");
break;
}
nes_write_indexed(nesdev, NES_IDX_GPR_TRIGGER, 1);
}
if (counter == NES_PAU_COUNTER) {
printk(KERN_INFO PFX "PAU is not supported.\n");
return -EPERM;
}
return ret;
}
/**
* nes_read_eeprom_values -
*/
int nes_read_eeprom_values(struct nes_device *nesdev, struct nes_adapter *nesadapter)
{
u32 mac_addr_low;
u16 mac_addr_high;
u16 eeprom_data;
u16 eeprom_offset;
u16 next_section_address;
u16 sw_section_ver;
u8 major_ver = 0;
u8 minor_ver = 0;
/* TODO: deal with EEPROM endian issues */
if (nesadapter->firmware_eeprom_offset == 0) {
/* Read the EEPROM Parameters */
eeprom_data = nes_read16_eeprom(nesdev->regs, 0);
nes_debug(NES_DBG_HW, "EEPROM Offset 0 = 0x%04X\n", eeprom_data);
eeprom_offset = 2 + (((eeprom_data & 0x007f) << 3) <<
((eeprom_data & 0x0080) >> 7));
nes_debug(NES_DBG_HW, "Firmware Offset = 0x%04X\n", eeprom_offset);
nesadapter->firmware_eeprom_offset = eeprom_offset;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 4);
if (eeprom_data != 0x5746) {
nes_debug(NES_DBG_HW, "Not a valid Firmware Image = 0x%04X\n", eeprom_data);
return -1;
}
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
nes_debug(NES_DBG_HW, "EEPROM Offset %u = 0x%04X\n",
eeprom_offset + 2, eeprom_data);
eeprom_offset += ((eeprom_data & 0x00ff) << 3) << ((eeprom_data & 0x0100) >> 8);
nes_debug(NES_DBG_HW, "Software Offset = 0x%04X\n", eeprom_offset);
nesadapter->software_eeprom_offset = eeprom_offset;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 4);
if (eeprom_data != 0x5753) {
printk("Not a valid Software Image = 0x%04X\n", eeprom_data);
return -1;
}
sw_section_ver = nes_read16_eeprom(nesdev->regs, nesadapter->software_eeprom_offset + 6);
nes_debug(NES_DBG_HW, "Software section version number = 0x%04X\n",
sw_section_ver);
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
eeprom_offset + 2, eeprom_data);
next_section_address = eeprom_offset + (((eeprom_data & 0x00ff) << 3) <<
((eeprom_data & 0x0100) >> 8));
eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
if (eeprom_data != 0x414d) {
nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x414d but was 0x%04X\n",
eeprom_data);
goto no_fw_rev;
}
eeprom_offset = next_section_address;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
eeprom_offset + 2, eeprom_data);
next_section_address = eeprom_offset + (((eeprom_data & 0x00ff) << 3) <<
((eeprom_data & 0x0100) >> 8));
eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
if (eeprom_data != 0x4f52) {
nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x4f52 but was 0x%04X\n",
eeprom_data);
goto no_fw_rev;
}
eeprom_offset = next_section_address;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
eeprom_offset + 2, eeprom_data);
next_section_address = eeprom_offset + ((eeprom_data & 0x00ff) << 3);
eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
if (eeprom_data != 0x5746) {
nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x5746 but was 0x%04X\n",
eeprom_data);
goto no_fw_rev;
}
eeprom_offset = next_section_address;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
eeprom_offset + 2, eeprom_data);
next_section_address = eeprom_offset + ((eeprom_data & 0x00ff) << 3);
eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
if (eeprom_data != 0x5753) {
nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x5753 but was 0x%04X\n",
eeprom_data);
goto no_fw_rev;
}
eeprom_offset = next_section_address;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
eeprom_offset + 2, eeprom_data);
next_section_address = eeprom_offset + ((eeprom_data & 0x00ff) << 3);
eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
if (eeprom_data != 0x414d) {
nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x414d but was 0x%04X\n",
eeprom_data);
goto no_fw_rev;
}
eeprom_offset = next_section_address;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset + 2);
nes_debug(NES_DBG_HW, "EEPROM Offset %u (next section) = 0x%04X\n",
eeprom_offset + 2, eeprom_data);
next_section_address = eeprom_offset + ((eeprom_data & 0x00ff) << 3);
eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 4);
if (eeprom_data != 0x464e) {
nes_debug(NES_DBG_HW, "EEPROM Changed offset should be 0x464e but was 0x%04X\n",
eeprom_data);
goto no_fw_rev;
}
eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 8);
printk(PFX "Firmware version %u.%u\n", (u8)(eeprom_data>>8), (u8)eeprom_data);
major_ver = (u8)(eeprom_data >> 8);
minor_ver = (u8)(eeprom_data);
if (nes_drv_opt & NES_DRV_OPT_DISABLE_VIRT_WQ) {
nes_debug(NES_DBG_HW, "Virtual WQs have been disabled\n");
} else if (((major_ver == 2) && (minor_ver > 21)) || ((major_ver > 2) && (major_ver != 255))) {
nesadapter->virtwq = 1;
}
if (((major_ver == 3) && (minor_ver >= 16)) || (major_ver > 3))
nesadapter->send_term_ok = 1;
if (nes_drv_opt & NES_DRV_OPT_ENABLE_PAU) {
if (!nes_set_pau(nesdev))
nesadapter->allow_unaligned_fpdus = 1;
}
nesadapter->firmware_version = (((u32)(u8)(eeprom_data>>8)) << 16) +
(u32)((u8)eeprom_data);
eeprom_data = nes_read16_eeprom(nesdev->regs, next_section_address + 10);
printk(PFX "EEPROM version %u.%u\n", (u8)(eeprom_data>>8), (u8)eeprom_data);
nesadapter->eeprom_version = (((u32)(u8)(eeprom_data>>8)) << 16) +
(u32)((u8)eeprom_data);
no_fw_rev:
/* eeprom is valid */
eeprom_offset = nesadapter->software_eeprom_offset;
eeprom_offset += 8;
nesadapter->netdev_max = (u8)nes_read16_eeprom(nesdev->regs, eeprom_offset);
eeprom_offset += 2;
mac_addr_high = nes_read16_eeprom(nesdev->regs, eeprom_offset);
eeprom_offset += 2;
mac_addr_low = (u32)nes_read16_eeprom(nesdev->regs, eeprom_offset);
eeprom_offset += 2;
mac_addr_low <<= 16;
mac_addr_low += (u32)nes_read16_eeprom(nesdev->regs, eeprom_offset);
nes_debug(NES_DBG_HW, "Base MAC Address = 0x%04X%08X\n",
mac_addr_high, mac_addr_low);
nes_debug(NES_DBG_HW, "MAC Address count = %u\n", nesadapter->netdev_max);
nesadapter->mac_addr_low = mac_addr_low;
nesadapter->mac_addr_high = mac_addr_high;
/* Read the Phy Type array */
eeprom_offset += 10;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
nesadapter->phy_type[0] = (u8)(eeprom_data >> 8);
nesadapter->phy_type[1] = (u8)eeprom_data;
/* Read the port array */
eeprom_offset += 2;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
nesadapter->phy_type[2] = (u8)(eeprom_data >> 8);
nesadapter->phy_type[3] = (u8)eeprom_data;
/* port_count is set by soft reset reg */
nes_debug(NES_DBG_HW, "port_count = %u, port 0 -> %u, port 1 -> %u,"
" port 2 -> %u, port 3 -> %u\n",
nesadapter->port_count,
nesadapter->phy_type[0], nesadapter->phy_type[1],
nesadapter->phy_type[2], nesadapter->phy_type[3]);
/* Read PD config array */
eeprom_offset += 10;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
nesadapter->pd_config_size[0] = eeprom_data;
eeprom_offset += 2;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
nesadapter->pd_config_base[0] = eeprom_data;
nes_debug(NES_DBG_HW, "PD0 config, size=0x%04x, base=0x%04x\n",
nesadapter->pd_config_size[0], nesadapter->pd_config_base[0]);
eeprom_offset += 2;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
nesadapter->pd_config_size[1] = eeprom_data;
eeprom_offset += 2;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
nesadapter->pd_config_base[1] = eeprom_data;
nes_debug(NES_DBG_HW, "PD1 config, size=0x%04x, base=0x%04x\n",
nesadapter->pd_config_size[1], nesadapter->pd_config_base[1]);
eeprom_offset += 2;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
nesadapter->pd_config_size[2] = eeprom_data;
eeprom_offset += 2;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
nesadapter->pd_config_base[2] = eeprom_data;
nes_debug(NES_DBG_HW, "PD2 config, size=0x%04x, base=0x%04x\n",
nesadapter->pd_config_size[2], nesadapter->pd_config_base[2]);
eeprom_offset += 2;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
nesadapter->pd_config_size[3] = eeprom_data;
eeprom_offset += 2;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
nesadapter->pd_config_base[3] = eeprom_data;
nes_debug(NES_DBG_HW, "PD3 config, size=0x%04x, base=0x%04x\n",
nesadapter->pd_config_size[3], nesadapter->pd_config_base[3]);
/* Read Rx Pool Size */
eeprom_offset += 22; /* 46 */
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
eeprom_offset += 2;
nesadapter->rx_pool_size = (((u32)eeprom_data) << 16) +
nes_read16_eeprom(nesdev->regs, eeprom_offset);
nes_debug(NES_DBG_HW, "rx_pool_size = 0x%08X\n", nesadapter->rx_pool_size);
eeprom_offset += 2;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
eeprom_offset += 2;
nesadapter->tx_pool_size = (((u32)eeprom_data) << 16) +
nes_read16_eeprom(nesdev->regs, eeprom_offset);
nes_debug(NES_DBG_HW, "tx_pool_size = 0x%08X\n", nesadapter->tx_pool_size);
eeprom_offset += 2;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
eeprom_offset += 2;
nesadapter->rx_threshold = (((u32)eeprom_data) << 16) +
nes_read16_eeprom(nesdev->regs, eeprom_offset);
nes_debug(NES_DBG_HW, "rx_threshold = 0x%08X\n", nesadapter->rx_threshold);
eeprom_offset += 2;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
eeprom_offset += 2;
nesadapter->tcp_timer_core_clk_divisor = (((u32)eeprom_data) << 16) +
nes_read16_eeprom(nesdev->regs, eeprom_offset);
nes_debug(NES_DBG_HW, "tcp_timer_core_clk_divisor = 0x%08X\n",
nesadapter->tcp_timer_core_clk_divisor);
eeprom_offset += 2;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
eeprom_offset += 2;
nesadapter->iwarp_config = (((u32)eeprom_data) << 16) +
nes_read16_eeprom(nesdev->regs, eeprom_offset);
nes_debug(NES_DBG_HW, "iwarp_config = 0x%08X\n", nesadapter->iwarp_config);
eeprom_offset += 2;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
eeprom_offset += 2;
nesadapter->cm_config = (((u32)eeprom_data) << 16) +
nes_read16_eeprom(nesdev->regs, eeprom_offset);
nes_debug(NES_DBG_HW, "cm_config = 0x%08X\n", nesadapter->cm_config);
eeprom_offset += 2;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
eeprom_offset += 2;
nesadapter->sws_timer_config = (((u32)eeprom_data) << 16) +
nes_read16_eeprom(nesdev->regs, eeprom_offset);
nes_debug(NES_DBG_HW, "sws_timer_config = 0x%08X\n", nesadapter->sws_timer_config);
eeprom_offset += 2;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
eeprom_offset += 2;
nesadapter->tcp_config1 = (((u32)eeprom_data) << 16) +
nes_read16_eeprom(nesdev->regs, eeprom_offset);
nes_debug(NES_DBG_HW, "tcp_config1 = 0x%08X\n", nesadapter->tcp_config1);
eeprom_offset += 2;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
eeprom_offset += 2;
nesadapter->wqm_wat = (((u32)eeprom_data) << 16) +
nes_read16_eeprom(nesdev->regs, eeprom_offset);
nes_debug(NES_DBG_HW, "wqm_wat = 0x%08X\n", nesadapter->wqm_wat);
eeprom_offset += 2;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
eeprom_offset += 2;
nesadapter->core_clock = (((u32)eeprom_data) << 16) +
nes_read16_eeprom(nesdev->regs, eeprom_offset);
nes_debug(NES_DBG_HW, "core_clock = 0x%08X\n", nesadapter->core_clock);
if ((sw_section_ver) && (nesadapter->hw_rev != NE020_REV)) {
eeprom_offset += 2;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
nesadapter->phy_index[0] = (eeprom_data & 0xff00)>>8;
nesadapter->phy_index[1] = eeprom_data & 0x00ff;
eeprom_offset += 2;
eeprom_data = nes_read16_eeprom(nesdev->regs, eeprom_offset);
nesadapter->phy_index[2] = (eeprom_data & 0xff00)>>8;
nesadapter->phy_index[3] = eeprom_data & 0x00ff;
} else {
nesadapter->phy_index[0] = 4;
nesadapter->phy_index[1] = 5;
nesadapter->phy_index[2] = 6;
nesadapter->phy_index[3] = 7;
}
nes_debug(NES_DBG_HW, "Phy address map = 0 > %u, 1 > %u, 2 > %u, 3 > %u\n",
nesadapter->phy_index[0],nesadapter->phy_index[1],
nesadapter->phy_index[2],nesadapter->phy_index[3]);
}
return 0;
}
/**
* nes_read16_eeprom
*/
static u16 nes_read16_eeprom(void __iomem *addr, u16 offset)
{
writel(NES_EEPROM_READ_REQUEST + (offset >> 1),
(void __iomem *)addr + NES_EEPROM_COMMAND);
do {
} while (readl((void __iomem *)addr + NES_EEPROM_COMMAND) &
NES_EEPROM_READ_REQUEST);
return readw((void __iomem *)addr + NES_EEPROM_DATA);
}
/**
* nes_write_1G_phy_reg
*/
void nes_write_1G_phy_reg(struct nes_device *nesdev, u8 phy_reg, u8 phy_addr, u16 data)
{
u32 u32temp;
u32 counter;
nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
0x50020000 | data | ((u32)phy_reg << 18) | ((u32)phy_addr << 23));
for (counter = 0; counter < 100 ; counter++) {
udelay(30);
u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
if (u32temp & 1) {
/* nes_debug(NES_DBG_PHY, "Phy interrupt status = 0x%X.\n", u32temp); */
nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
break;
}
}
if (!(u32temp & 1))
nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
u32temp);
}
/**
* nes_read_1G_phy_reg
* This routine only issues the read, the data must be read
* separately.
*/
void nes_read_1G_phy_reg(struct nes_device *nesdev, u8 phy_reg, u8 phy_addr, u16 *data)
{
u32 u32temp;
u32 counter;
/* nes_debug(NES_DBG_PHY, "phy addr = %d, mac_index = %d\n",
phy_addr, nesdev->mac_index); */
nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
0x60020000 | ((u32)phy_reg << 18) | ((u32)phy_addr << 23));
for (counter = 0; counter < 100 ; counter++) {
udelay(30);
u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
if (u32temp & 1) {
/* nes_debug(NES_DBG_PHY, "Phy interrupt status = 0x%X.\n", u32temp); */
nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
break;
}
}
if (!(u32temp & 1)) {
nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
u32temp);
*data = 0xffff;
} else {
*data = (u16)nes_read_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL);
}
}
/**
* nes_write_10G_phy_reg
*/
void nes_write_10G_phy_reg(struct nes_device *nesdev, u16 phy_addr, u8 dev_addr, u16 phy_reg,
u16 data)
{
u32 port_addr;
u32 u32temp;
u32 counter;
port_addr = phy_addr;
/* set address */
nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
0x00020000 | (u32)phy_reg | (((u32)dev_addr) << 18) | (((u32)port_addr) << 23));
for (counter = 0; counter < 100 ; counter++) {
udelay(30);
u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
if (u32temp & 1) {
nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
break;
}
}
if (!(u32temp & 1))
nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
u32temp);
/* set data */
nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
0x10020000 | (u32)data | (((u32)dev_addr) << 18) | (((u32)port_addr) << 23));
for (counter = 0; counter < 100 ; counter++) {
udelay(30);
u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
if (u32temp & 1) {
nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
break;
}
}
if (!(u32temp & 1))
nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
u32temp);
}
/**
* nes_read_10G_phy_reg
* This routine only issues the read, the data must be read
* separately.
*/
void nes_read_10G_phy_reg(struct nes_device *nesdev, u8 phy_addr, u8 dev_addr, u16 phy_reg)
{
u32 port_addr;
u32 u32temp;
u32 counter;
port_addr = phy_addr;
/* set address */
nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
0x00020000 | (u32)phy_reg | (((u32)dev_addr) << 18) | (((u32)port_addr) << 23));
for (counter = 0; counter < 100 ; counter++) {
udelay(30);
u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
if (u32temp & 1) {
nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
break;
}
}
if (!(u32temp & 1))
nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
u32temp);
/* issue read */
nes_write_indexed(nesdev, NES_IDX_MAC_MDIO_CONTROL,
0x30020000 | (((u32)dev_addr) << 18) | (((u32)port_addr) << 23));
for (counter = 0; counter < 100 ; counter++) {
udelay(30);
u32temp = nes_read_indexed(nesdev, NES_IDX_MAC_INT_STATUS);
if (u32temp & 1) {
nes_write_indexed(nesdev, NES_IDX_MAC_INT_STATUS, 1);
break;
}
}
if (!(u32temp & 1))
nes_debug(NES_DBG_PHY, "Phy is not responding. interrupt status = 0x%X.\n",
u32temp);
}
/**
* nes_get_cqp_request
*/
struct nes_cqp_request *nes_get_cqp_request(struct nes_device *nesdev)
{
unsigned long flags;
struct nes_cqp_request *cqp_request = NULL;
if (!list_empty(&nesdev->cqp_avail_reqs)) {
spin_lock_irqsave(&nesdev->cqp.lock, flags);
if (!list_empty(&nesdev->cqp_avail_reqs)) {
cqp_request = list_entry(nesdev->cqp_avail_reqs.next,
struct nes_cqp_request, list);
list_del_init(&cqp_request->list);
}
spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
}
if (cqp_request == NULL) {
cqp_request = kzalloc(sizeof(struct nes_cqp_request), GFP_ATOMIC);
if (cqp_request) {
cqp_request->dynamic = 1;
INIT_LIST_HEAD(&cqp_request->list);
}
}
if (cqp_request) {
init_waitqueue_head(&cqp_request->waitq);
cqp_request->waiting = 0;
cqp_request->request_done = 0;
cqp_request->callback = 0;
nes_debug(NES_DBG_CQP, "Got cqp request %p from the available list \n",
cqp_request);
}
return cqp_request;
}
void nes_free_cqp_request(struct nes_device *nesdev,
struct nes_cqp_request *cqp_request)
{
unsigned long flags;
nes_debug(NES_DBG_CQP, "CQP request %p (opcode 0x%02X) freed.\n",
cqp_request,
le32_to_cpu(cqp_request->cqp_wqe.wqe_words[NES_CQP_WQE_OPCODE_IDX]) & 0x3f);
if (cqp_request->dynamic) {
kfree(cqp_request);
} else {
spin_lock_irqsave(&nesdev->cqp.lock, flags);
list_add_tail(&cqp_request->list, &nesdev->cqp_avail_reqs);
spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
}
}
void nes_put_cqp_request(struct nes_device *nesdev,
struct nes_cqp_request *cqp_request)
{
if (atomic_dec_and_test(&cqp_request->refcount))
nes_free_cqp_request(nesdev, cqp_request);
}
/**
* nes_post_cqp_request
*/
void nes_post_cqp_request(struct nes_device *nesdev,
struct nes_cqp_request *cqp_request)
{
struct nes_hw_cqp_wqe *cqp_wqe;
unsigned long flags;
u32 cqp_head;
u64 u64temp;
u32 opcode;
int ctx_index = NES_CQP_WQE_COMP_CTX_LOW_IDX;
spin_lock_irqsave(&nesdev->cqp.lock, flags);
if (((((nesdev->cqp.sq_tail+(nesdev->cqp.sq_size*2))-nesdev->cqp.sq_head) &
(nesdev->cqp.sq_size - 1)) != 1)
&& (list_empty(&nesdev->cqp_pending_reqs))) {
cqp_head = nesdev->cqp.sq_head++;
nesdev->cqp.sq_head &= nesdev->cqp.sq_size-1;
cqp_wqe = &nesdev->cqp.sq_vbase[cqp_head];
memcpy(cqp_wqe, &cqp_request->cqp_wqe, sizeof(*cqp_wqe));
opcode = le32_to_cpu(cqp_wqe->wqe_words[NES_CQP_WQE_OPCODE_IDX]);
if ((opcode & NES_CQP_OPCODE_MASK) == NES_CQP_DOWNLOAD_SEGMENT)
ctx_index = NES_CQP_WQE_DL_COMP_CTX_LOW_IDX;
barrier();
u64temp = (unsigned long)cqp_request;
set_wqe_64bit_value(cqp_wqe->wqe_words, ctx_index, u64temp);
nes_debug(NES_DBG_CQP, "CQP request (opcode 0x%02X), line 1 = 0x%08X put on CQPs SQ,"
" request = %p, cqp_head = %u, cqp_tail = %u, cqp_size = %u,"
" waiting = %d, refcount = %d.\n",
opcode & NES_CQP_OPCODE_MASK,
le32_to_cpu(cqp_wqe->wqe_words[NES_CQP_WQE_ID_IDX]), cqp_request,
nesdev->cqp.sq_head, nesdev->cqp.sq_tail, nesdev->cqp.sq_size,
cqp_request->waiting, atomic_read(&cqp_request->refcount));
barrier();
/* Ring doorbell (1 WQEs) */
nes_write32(nesdev->regs+NES_WQE_ALLOC, 0x01800000 | nesdev->cqp.qp_id);
barrier();
} else {
nes_debug(NES_DBG_CQP, "CQP request %p (opcode 0x%02X), line 1 = 0x%08X"
" put on the pending queue.\n",
cqp_request,
le32_to_cpu(cqp_request->cqp_wqe.wqe_words[NES_CQP_WQE_OPCODE_IDX])&0x3f,
le32_to_cpu(cqp_request->cqp_wqe.wqe_words[NES_CQP_WQE_ID_IDX]));
list_add_tail(&cqp_request->list, &nesdev->cqp_pending_reqs);
}
spin_unlock_irqrestore(&nesdev->cqp.lock, flags);
return;
}
/**
* nes_arp_table
*/
int nes_arp_table(struct nes_device *nesdev, u32 ip_addr, u8 *mac_addr, u32 action)
{
struct nes_adapter *nesadapter = nesdev->nesadapter;
int arp_index;
int err = 0;
__be32 tmp_addr;
for (arp_index = 0; (u32) arp_index < nesadapter->arp_table_size; arp_index++) {
if (nesadapter->arp_table[arp_index].ip_addr == ip_addr)
break;
}
if (action == NES_ARP_ADD) {
if (arp_index != nesadapter->arp_table_size) {
return -1;
}
arp_index = 0;
err = nes_alloc_resource(nesadapter, nesadapter->allocated_arps,
nesadapter->arp_table_size, (u32 *)&arp_index, &nesadapter->next_arp_index, NES_RESOURCE_ARP);
if (err) {
nes_debug(NES_DBG_NETDEV, "nes_alloc_resource returned error = %u\n", err);
return err;
}
nes_debug(NES_DBG_NETDEV, "ADD, arp_index=%d\n", arp_index);
nesadapter->arp_table[arp_index].ip_addr = ip_addr;
memcpy(nesadapter->arp_table[arp_index].mac_addr, mac_addr, ETH_ALEN);
return arp_index;
}
/* DELETE or RESOLVE */
if (arp_index == nesadapter->arp_table_size) {
tmp_addr = cpu_to_be32(ip_addr);
nes_debug(NES_DBG_NETDEV, "MAC for %pI4 not in ARP table - cannot %s\n",
&tmp_addr, action == NES_ARP_RESOLVE ? "resolve" : "delete");
return -1;
}
if (action == NES_ARP_RESOLVE) {
nes_debug(NES_DBG_NETDEV, "RESOLVE, arp_index=%d\n", arp_index);
return arp_index;
}
if (action == NES_ARP_DELETE) {
nes_debug(NES_DBG_NETDEV, "DELETE, arp_index=%d\n", arp_index);
nesadapter->arp_table[arp_index].ip_addr = 0;
eth_zero_addr(nesadapter->arp_table[arp_index].mac_addr);
nes_free_resource(nesadapter, nesadapter->allocated_arps, arp_index);
return arp_index;
}
return -1;
}
/**
* nes_mh_fix
*/
void nes_mh_fix(struct timer_list *t)
{
struct nes_adapter *nesadapter = from_timer(nesadapter, t, mh_timer);
struct nes_device *nesdev = nesadapter->nesdev;
unsigned long flags;
struct nes_vnic *nesvnic;
u32 used_chunks_tx;
u32 temp_used_chunks_tx;
u32 temp_last_used_chunks_tx;
u32 used_chunks_mask;
u32 mac_tx_frames_low;
u32 mac_tx_frames_high;
u32 mac_tx_pauses;
u32 reset_value;
u32 tx_control;
u32 tx_config;
u32 tx_pause_quanta;
u32 rx_control;
u32 rx_config;
u32 mac_exact_match;
u32 mpp_debug;
u32 i=0;
u32 chunks_tx_progress = 0;
spin_lock_irqsave(&nesadapter->phy_lock, flags);
if ((nesadapter->mac_sw_state[0] != NES_MAC_SW_IDLE) || (nesadapter->mac_link_down[0])) {
spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
goto no_mh_work;
}
nesadapter->mac_sw_state[0] = NES_MAC_SW_MH;
spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
do {
mac_tx_frames_low = nes_read_indexed(nesdev, NES_IDX_MAC_TX_FRAMES_LOW);
mac_tx_frames_high = nes_read_indexed(nesdev, NES_IDX_MAC_TX_FRAMES_HIGH);
mac_tx_pauses = nes_read_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_FRAMES);
used_chunks_tx = nes_read_indexed(nesdev, NES_IDX_USED_CHUNKS_TX);
nesdev->mac_pause_frames_sent += mac_tx_pauses;
used_chunks_mask = 0;
temp_used_chunks_tx = used_chunks_tx;
temp_last_used_chunks_tx = nesdev->last_used_chunks_tx;
if (nesdev->netdev[0]) {
nesvnic = netdev_priv(nesdev->netdev[0]);
} else {
break;
}
for (i=0; i<4; i++) {
used_chunks_mask <<= 8;
if (nesvnic->qp_nic_index[i] != 0xff) {
used_chunks_mask |= 0xff;
if ((temp_used_chunks_tx&0xff)<(temp_last_used_chunks_tx&0xff)) {
chunks_tx_progress = 1;
}
}
temp_used_chunks_tx >>= 8;
temp_last_used_chunks_tx >>= 8;
}
if ((mac_tx_frames_low) || (mac_tx_frames_high) ||
(!(used_chunks_tx&used_chunks_mask)) ||
(!(nesdev->last_used_chunks_tx&used_chunks_mask)) ||
(chunks_tx_progress) ) {
nesdev->last_used_chunks_tx = used_chunks_tx;
break;
}
nesdev->last_used_chunks_tx = used_chunks_tx;
barrier();
nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONTROL, 0x00000005);
mh_pauses_sent++;
mac_tx_pauses = nes_read_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_FRAMES);
if (mac_tx_pauses) {
nesdev->mac_pause_frames_sent += mac_tx_pauses;
break;
}
tx_control = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONTROL);
tx_config = nes_read_indexed(nesdev, NES_IDX_MAC_TX_CONFIG);
tx_pause_quanta = nes_read_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_QUANTA);
rx_control = nes_read_indexed(nesdev, NES_IDX_MAC_RX_CONTROL);
rx_config = nes_read_indexed(nesdev, NES_IDX_MAC_RX_CONFIG);
mac_exact_match = nes_read_indexed(nesdev, NES_IDX_MAC_EXACT_MATCH_BOTTOM);
mpp_debug = nes_read_indexed(nesdev, NES_IDX_MPP_DEBUG);
/* one last ditch effort to avoid a false positive */
mac_tx_pauses = nes_read_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_FRAMES);
if (mac_tx_pauses) {
nesdev->last_mac_tx_pauses = nesdev->mac_pause_frames_sent;
nes_debug(NES_DBG_HW, "failsafe caught slow outbound pause\n");
break;
}
mh_detected++;
nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONTROL, 0x00000000);
nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, 0x00000000);
reset_value = nes_read32(nesdev->regs+NES_SOFTWARE_RESET);
nes_write32(nesdev->regs+NES_SOFTWARE_RESET, reset_value | 0x0000001d);
while (((nes_read32(nesdev->regs+NES_SOFTWARE_RESET)
& 0x00000040) != 0x00000040) && (i++ < 5000)) {
/* mdelay(1); */
}
nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_CONTROL0, 0x00000008);
nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_COMMON_STATUS0);
nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_EMP0, 0x000bdef7);
nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_TX_DRIVE0, 0x9ce73000);
nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_MODE0, 0x0ff00000);
nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_SIGDET0, 0x00000000);
nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_BYPASS0, 0x00000000);
nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_LOOPBACK_CONTROL0, 0x00000000);
if (nesadapter->OneG_Mode) {
nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_CONTROL0, 0xf0182222);
} else {
nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_CONTROL0, 0xf0042222);
}
nes_read_indexed(nesdev, NES_IDX_ETH_SERDES_RX_EQ_STATUS0);
nes_write_indexed(nesdev, NES_IDX_ETH_SERDES_CDR_CONTROL0, 0x000000ff);
nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONTROL, tx_control);
nes_write_indexed(nesdev, NES_IDX_MAC_TX_CONFIG, tx_config);
nes_write_indexed(nesdev, NES_IDX_MAC_TX_PAUSE_QUANTA, tx_pause_quanta);
nes_write_indexed(nesdev, NES_IDX_MAC_RX_CONTROL, rx_control);
nes_write_indexed(nesdev, NES_IDX_MAC_RX_CONFIG, rx_config);
nes_write_indexed(nesdev, NES_IDX_MAC_EXACT_MATCH_BOTTOM, mac_exact_match);
nes_write_indexed(nesdev, NES_IDX_MPP_DEBUG, mpp_debug);
} while (0);
nesadapter->mac_sw_state[0] = NES_MAC_SW_IDLE;
no_mh_work:
nesdev->nesadapter->mh_timer.expires = jiffies + (HZ/5);
add_timer(&nesdev->nesadapter->mh_timer);
}
/**
* nes_clc
*/
void nes_clc(struct timer_list *t)
{
struct nes_adapter *nesadapter = from_timer(nesadapter, t, lc_timer);
unsigned long flags;
spin_lock_irqsave(&nesadapter->phy_lock, flags);
nesadapter->link_interrupt_count[0] = 0;
nesadapter->link_interrupt_count[1] = 0;
nesadapter->link_interrupt_count[2] = 0;
nesadapter->link_interrupt_count[3] = 0;
spin_unlock_irqrestore(&nesadapter->phy_lock, flags);
nesadapter->lc_timer.expires = jiffies + 3600 * HZ; /* 1 hour */
add_timer(&nesadapter->lc_timer);
}
/**
* nes_dump_mem
*/
void nes_dump_mem(unsigned int dump_debug_level, void *addr, int length)
{
if (!(nes_debug_level & dump_debug_level)) {
return;
}
if (length > 0x100) {
nes_debug(dump_debug_level, "Length truncated from %x to %x\n", length, 0x100);
length = 0x100;
}
nes_debug(dump_debug_level, "Address=0x%p, length=0x%x (%d)\n", addr, length, length);
print_hex_dump(KERN_ERR, PFX, DUMP_PREFIX_NONE, 16, 1, addr, length, true);
}

3721
drivers/infiniband/hw/nes/nes_verbs.c
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File diff suppressed because it is too large Load Diff

198
drivers/infiniband/hw/nes/nes_verbs.h
View File

@ -1,198 +0,0 @@
/*
* Copyright (c) 2006 - 2011 Intel Corporation. All rights reserved.
* Copyright (c) 2005 Open Grid Computing, Inc. All rights reserved.
*
* This software is available to you under a choice of one of two
* licenses. You may choose to be licensed under the terms of the GNU
* General Public License (GPL) Version 2, available from the file
* COPYING in the main directory of this source tree, or the
* OpenIB.org BSD license below:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* - Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* - Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*
*/
#ifndef NES_VERBS_H
#define NES_VERBS_H
struct nes_device;
#define NES_MAX_USER_DB_REGIONS 4096
#define NES_MAX_USER_WQ_REGIONS 4096
#define NES_TERM_SENT 0x01
#define NES_TERM_RCVD 0x02
#define NES_TERM_DONE 0x04
struct nes_ucontext {
struct ib_ucontext ibucontext;
struct nes_device *nesdev;
unsigned long mmap_wq_offset;
unsigned long mmap_cq_offset; /* to be removed */
int index; /* rnic index (minor) */
unsigned long allocated_doorbells[BITS_TO_LONGS(NES_MAX_USER_DB_REGIONS)];
u16 mmap_db_index[NES_MAX_USER_DB_REGIONS];
u16 first_free_db;
unsigned long allocated_wqs[BITS_TO_LONGS(NES_MAX_USER_WQ_REGIONS)];
struct nes_qp *mmap_nesqp[NES_MAX_USER_WQ_REGIONS];
u16 first_free_wq;
struct list_head cq_reg_mem_list;
struct list_head qp_reg_mem_list;
u32 mcrqf;
};
struct nes_pd {
struct ib_pd ibpd;
u16 pd_id;
atomic_t sqp_count;
u16 mmap_db_index;
};
struct nes_mr {
union {
struct ib_mr ibmr;
struct ib_mw ibmw;
struct ib_fmr ibfmr;
};
struct ib_umem *region;
u16 pbls_used;
u8 mode;
u8 pbl_4k;
__le64 *pages;
dma_addr_t paddr;
u32 max_pages;
u32 npages;
};
struct nes_hw_pb {
__le32 pa_low;
__le32 pa_high;
};
struct nes_vpbl {
dma_addr_t pbl_pbase;
struct nes_hw_pb *pbl_vbase;
};
struct nes_root_vpbl {
dma_addr_t pbl_pbase;
struct nes_hw_pb *pbl_vbase;
struct nes_vpbl *leaf_vpbl;
};
struct nes_fmr {
struct nes_mr nesmr;
u32 leaf_pbl_cnt;
struct nes_root_vpbl root_vpbl;
struct ib_qp *ib_qp;
int access_rights;
struct ib_fmr_attr attr;
};
struct nes_av;
struct nes_cq {
struct ib_cq ibcq;
struct nes_hw_cq hw_cq;
u32 polled_completions;
u32 cq_mem_size;
spinlock_t lock;
u8 virtual_cq;
u8 pad[3];
u32 mcrqf;
};
struct nes_wq {
spinlock_t lock;
};
struct disconn_work {
struct work_struct work;
struct nes_qp *nesqp;
};
struct iw_cm_id;
struct ietf_mpa_frame;
struct nes_qp {
struct ib_qp ibqp;
void *allocated_buffer;
struct iw_cm_id *cm_id;
struct nes_cq *nesscq;
struct nes_cq *nesrcq;
struct nes_pd *nespd;
void *cm_node; /* handle of the node this QP is associated with */
void *ietf_frame;
u8 ietf_frame_size;
dma_addr_t ietf_frame_pbase;
struct ib_mr *lsmm_mr;
struct nes_hw_qp hwqp;
struct work_struct work;
enum ib_qp_state ibqp_state;
u32 iwarp_state;
u32 hte_index;
u32 last_aeq;
u32 qp_mem_size;
atomic_t refcount;
atomic_t close_timer_started;
u32 mmap_sq_db_index;
u32 mmap_rq_db_index;
spinlock_t lock;
spinlock_t pau_lock;
struct nes_qp_context *nesqp_context;
dma_addr_t nesqp_context_pbase;
void *pbl_vbase;
dma_addr_t pbl_pbase;
struct page *page;
struct timer_list terminate_timer;
enum ib_event_type terminate_eventtype;
struct sk_buff_head pau_list;
u32 pau_rcv_nxt;
u16 active_conn:1;
u16 skip_lsmm:1;
u16 user_mode:1;
u16 hte_added:1;
u16 flush_issued:1;
u16 destroyed:1;
u16 sig_all:1;
u16 pau_mode:1;
u16 rsvd:8;
u16 private_data_len;
u16 term_sq_flush_code;
u16 term_rq_flush_code;
u8 hw_iwarp_state;
u8 hw_tcp_state;
u8 term_flags;
u8 sq_kmapped;
u8 pau_busy;
u8 pau_pending;
u8 pau_state;
__u64 nesuqp_addr;
struct completion sq_drained;
struct completion rq_drained;
};
struct ib_mr *nes_reg_phys_mr(struct ib_pd *ib_pd,
u64 addr, u64 size, int acc, u64 *iova_start);
#endif /* NES_VERBS_H */