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ARM i.MX: remove now unnecessary argument from mxc_timer_init

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As the timer code now does a clk_get to get its clock we don't
need the struct clk argument anymore.
This also changes the alternative EPIT timer to do a clk_get.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
This commit is contained in:
Sascha Hauer 2012-05-16 12:29:53 +02:00
parent 1f152b48ea
commit 2cfb45188a
11 changed files with 33 additions and 32 deletions
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3
arch/arm/mach-imx/clk-imx1.c
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@ -108,8 +108,7 @@ int __init mx1_clocks_init(unsigned long fref)
clk_register_clkdev(clk[clk32], NULL, "mxc_rtc.0");
clk_register_clkdev(clk[clko], "clko", NULL);
mxc_timer_init(NULL, MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR),
MX1_TIM1_INT);
mxc_timer_init(MX1_IO_ADDRESS(MX1_TIM1_BASE_ADDR), MX1_TIM1_INT);
return 0;
}

4
arch/arm/mach-imx/clk-imx21.c
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@ -180,7 +180,7 @@ int __init mx21_clocks_init(unsigned long lref, unsigned long href)
clk_register_clkdev(clk[sdhc1_ipg_gate], "sdhc1", NULL);
clk_register_clkdev(clk[sdhc2_ipg_gate], "sdhc2", NULL);
mxc_timer_init(NULL, MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR),
MX21_INT_GPT1);
mxc_timer_init(MX21_IO_ADDRESS(MX21_GPT1_BASE_ADDR), MX21_INT_GPT1);
return 0;
}

2
arch/arm/mach-imx/clk-imx25.c
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@ -243,6 +243,6 @@ int __init mx25_clocks_init(void)
clk_register_clkdev(clk[sdma_ahb], "ahb", "imx35-sdma");
clk_register_clkdev(clk[iim_ipg], "iim", NULL);
mxc_timer_init(NULL, MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
mxc_timer_init(MX25_IO_ADDRESS(MX25_GPT1_BASE_ADDR), 54);
return 0;
}

3
arch/arm/mach-imx/clk-imx27.c
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@ -263,8 +263,7 @@ int __init mx27_clocks_init(unsigned long fref)
clk_register_clkdev(clk[ssi1_baud_gate], "bitrate" , "imx-ssi.0");
clk_register_clkdev(clk[ssi2_baud_gate], "bitrate" , "imx-ssi.1");
mxc_timer_init(NULL, MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR),
MX27_INT_GPT1);
mxc_timer_init(MX27_IO_ADDRESS(MX27_GPT1_BASE_ADDR), MX27_INT_GPT1);
clk_prepare_enable(clk[emi_ahb_gate]);

3
arch/arm/mach-imx/clk-imx31.c
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@ -175,8 +175,7 @@ int __init mx31_clocks_init(unsigned long fref)
mx31_revision();
clk_disable_unprepare(clk[iim_gate]);
mxc_timer_init(NULL, MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR),
MX31_INT_GPT);
mxc_timer_init(MX31_IO_ADDRESS(MX31_GPT1_BASE_ADDR), MX31_INT_GPT);
return 0;
}

6
arch/arm/mach-imx/clk-imx35.c
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@ -267,11 +267,9 @@ int __init mx35_clocks_init()
imx_print_silicon_rev("i.MX35", mx35_revision());
#ifdef CONFIG_MXC_USE_EPIT
epit_timer_init(&epit1_clk,
MX35_IO_ADDRESS(MX35_EPIT1_BASE_ADDR), MX35_INT_EPIT1);
epit_timer_init(MX35_IO_ADDRESS(MX35_EPIT1_BASE_ADDR), MX35_INT_EPIT1);
#else
mxc_timer_init(NULL, MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR),
MX35_INT_GPT);
mxc_timer_init(MX35_IO_ADDRESS(MX35_GPT1_BASE_ADDR), MX35_INT_GPT);
#endif
return 0;

6
arch/arm/mach-imx/clk-imx51-imx53.c
View File

@ -329,8 +329,7 @@ int __init mx51_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
clk_set_rate(clk[esdhc_b_podf], 166250000);
/* System timer */
mxc_timer_init(NULL, MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR),
MX51_INT_GPT);
mxc_timer_init(MX51_IO_ADDRESS(MX51_GPT1_BASE_ADDR), MX51_INT_GPT);
clk_prepare_enable(clk[iim_gate]);
imx_print_silicon_rev("i.MX51", mx51_revision());
@ -412,8 +411,7 @@ int __init mx53_clocks_init(unsigned long rate_ckil, unsigned long rate_osc,
clk_set_rate(clk[esdhc_b_podf], 200000000);
/* System timer */
mxc_timer_init(NULL, MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR),
MX53_INT_GPT);
mxc_timer_init(MX53_IO_ADDRESS(MX53_GPT1_BASE_ADDR), MX53_INT_GPT);
clk_prepare_enable(clk[iim_gate]);
imx_print_silicon_rev("i.MX53", mx53_revision());

2
arch/arm/mach-imx/clk-imx6q.c
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@ -433,7 +433,7 @@ int __init mx6q_clocks_init(void)
base = of_iomap(np, 0);
WARN_ON(!base);
irq = irq_of_parse_and_map(np, 0);
mxc_timer_init(NULL, base, irq);
mxc_timer_init(base, irq);
return 0;
}

11
arch/arm/plat-mxc/epit.c
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@ -50,6 +50,7 @@
#include <linux/irq.h>
#include <linux/clockchips.h>
#include <linux/clk.h>
#include <linux/err.h>
#include <mach/hardware.h>
#include <asm/mach/time.h>
@ -201,8 +202,16 @@ static int __init epit_clockevent_init(struct clk *timer_clk)
return 0;
}
void __init epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq)
void __init epit_timer_init(void __iomem *base, int irq)
{
struct clk *timer_clk;
timer_clk = clk_get_sys("imx-epit.0", NULL);
if (IS_ERR(timer_clk)) {
pr_err("i.MX epit: unable to get clk\n");
return;
}
clk_prepare_enable(timer_clk);
timer_base = base;

4
arch/arm/plat-mxc/include/mach/common.h
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@ -53,8 +53,8 @@ extern void imx35_soc_init(void);
extern void imx50_soc_init(void);
extern void imx51_soc_init(void);
extern void imx53_soc_init(void);
extern void epit_timer_init(struct clk *timer_clk, void __iomem *base, int irq);
extern void mxc_timer_init(struct clk *timer_clk, void __iomem *, int);
extern void epit_timer_init(void __iomem *base, int irq);
extern void mxc_timer_init(void __iomem *, int);
extern int mx1_clocks_init(unsigned long fref);
extern int mx21_clocks_init(unsigned long lref, unsigned long fref);
extern int mx25_clocks_init(void);

21
arch/arm/plat-mxc/time.c
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@ -281,23 +281,22 @@ static int __init mxc_clockevent_init(struct clk *timer_clk)
return 0;
}
void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq)
void __init mxc_timer_init(void __iomem *base, int irq)
{
uint32_t tctl_val;
struct clk *timer_clk;
struct clk *timer_ipg_clk;
if (!timer_clk) {
timer_clk = clk_get_sys("imx-gpt.0", "per");
if (IS_ERR(timer_clk)) {
pr_err("i.MX timer: unable to get clk\n");
return;
}
timer_ipg_clk = clk_get_sys("imx-gpt.0", "ipg");
if (!IS_ERR(timer_ipg_clk))
clk_prepare_enable(timer_ipg_clk);
timer_clk = clk_get_sys("imx-gpt.0", "per");
if (IS_ERR(timer_clk)) {
pr_err("i.MX timer: unable to get clk\n");
return;
}
timer_ipg_clk = clk_get_sys("imx-gpt.0", "ipg");
if (!IS_ERR(timer_ipg_clk))
clk_prepare_enable(timer_ipg_clk);
clk_prepare_enable(timer_clk);
timer_base = base;