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rt2800: add rt2800lib (part four)
Code unification. Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> Acked-by: Ivo van Doorn <IvDoorn@gmail.com> Acked-by: Gertjan van Wingerde <gwingerde@gmail.com> Signed-off-by: John W. Linville <linville@tuxdriver.com>
This commit is contained in:
parent
fcf5154118
commit
2ce3399521
@ -1658,3 +1658,160 @@ int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
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return 0;
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}
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EXPORT_SYMBOL_GPL(rt2800_init_rfcsr);
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/*
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* IEEE80211 stack callback functions.
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*/
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static void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
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u32 *iv32, u16 *iv16)
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{
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struct rt2x00_dev *rt2x00dev = hw->priv;
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struct mac_iveiv_entry iveiv_entry;
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u32 offset;
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offset = MAC_IVEIV_ENTRY(hw_key_idx);
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rt2800_register_multiread(rt2x00dev, offset,
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&iveiv_entry, sizeof(iveiv_entry));
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memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16));
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memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32));
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}
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static int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
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{
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struct rt2x00_dev *rt2x00dev = hw->priv;
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u32 reg;
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bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
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rt2800_register_read(rt2x00dev, TX_RTS_CFG, ®);
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rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, value);
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rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
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rt2800_register_read(rt2x00dev, CCK_PROT_CFG, ®);
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rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, enabled);
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rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
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rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®);
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rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, enabled);
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rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
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rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®);
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rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, enabled);
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rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
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rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®);
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rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, enabled);
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rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
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rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®);
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rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, enabled);
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rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
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rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®);
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rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, enabled);
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rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
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return 0;
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}
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static int rt2800_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
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const struct ieee80211_tx_queue_params *params)
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{
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struct rt2x00_dev *rt2x00dev = hw->priv;
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struct data_queue *queue;
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struct rt2x00_field32 field;
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int retval;
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u32 reg;
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u32 offset;
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/*
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* First pass the configuration through rt2x00lib, that will
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* update the queue settings and validate the input. After that
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* we are free to update the registers based on the value
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* in the queue parameter.
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*/
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retval = rt2x00mac_conf_tx(hw, queue_idx, params);
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if (retval)
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return retval;
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/*
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* We only need to perform additional register initialization
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* for WMM queues/
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*/
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if (queue_idx >= 4)
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return 0;
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queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
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/* Update WMM TXOP register */
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offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
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field.bit_offset = (queue_idx & 1) * 16;
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field.bit_mask = 0xffff << field.bit_offset;
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rt2800_register_read(rt2x00dev, offset, ®);
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rt2x00_set_field32(®, field, queue->txop);
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rt2800_register_write(rt2x00dev, offset, reg);
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/* Update WMM registers */
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field.bit_offset = queue_idx * 4;
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field.bit_mask = 0xf << field.bit_offset;
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rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, ®);
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rt2x00_set_field32(®, field, queue->aifs);
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rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
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rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, ®);
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rt2x00_set_field32(®, field, queue->cw_min);
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rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
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rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, ®);
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rt2x00_set_field32(®, field, queue->cw_max);
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rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
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/* Update EDCA registers */
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offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
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rt2800_register_read(rt2x00dev, offset, ®);
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rt2x00_set_field32(®, EDCA_AC0_CFG_TX_OP, queue->txop);
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rt2x00_set_field32(®, EDCA_AC0_CFG_AIFSN, queue->aifs);
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rt2x00_set_field32(®, EDCA_AC0_CFG_CWMIN, queue->cw_min);
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rt2x00_set_field32(®, EDCA_AC0_CFG_CWMAX, queue->cw_max);
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rt2800_register_write(rt2x00dev, offset, reg);
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return 0;
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}
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static u64 rt2800_get_tsf(struct ieee80211_hw *hw)
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{
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struct rt2x00_dev *rt2x00dev = hw->priv;
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u64 tsf;
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u32 reg;
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rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, ®);
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tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
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rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, ®);
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tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
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return tsf;
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}
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const struct ieee80211_ops rt2800_mac80211_ops = {
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.tx = rt2x00mac_tx,
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.start = rt2x00mac_start,
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.stop = rt2x00mac_stop,
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.add_interface = rt2x00mac_add_interface,
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.remove_interface = rt2x00mac_remove_interface,
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.config = rt2x00mac_config,
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.configure_filter = rt2x00mac_configure_filter,
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.set_tim = rt2x00mac_set_tim,
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.set_key = rt2x00mac_set_key,
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.get_stats = rt2x00mac_get_stats,
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.get_tkip_seq = rt2800_get_tkip_seq,
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.set_rts_threshold = rt2800_set_rts_threshold,
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.bss_info_changed = rt2x00mac_bss_info_changed,
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.conf_tx = rt2800_conf_tx,
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.get_tx_stats = rt2x00mac_get_tx_stats,
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.get_tsf = rt2800_get_tsf,
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.rfkill_poll = rt2x00mac_rfkill_poll,
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};
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EXPORT_SYMBOL_GPL(rt2800_mac80211_ops);
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@ -129,4 +129,6 @@ int rt2800_init_registers(struct rt2x00_dev *rt2x00dev);
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int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev);
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int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev);
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extern const struct ieee80211_ops rt2800_mac80211_ops;
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#endif /* RT2800LIB_H */
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@ -1513,161 +1513,6 @@ static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
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return 0;
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}
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/*
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* IEEE80211 stack callback functions.
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*/
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static void rt2800pci_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
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u32 *iv32, u16 *iv16)
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{
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struct rt2x00_dev *rt2x00dev = hw->priv;
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struct mac_iveiv_entry iveiv_entry;
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u32 offset;
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offset = MAC_IVEIV_ENTRY(hw_key_idx);
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rt2800_register_multiread(rt2x00dev, offset,
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&iveiv_entry, sizeof(iveiv_entry));
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memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16));
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memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32));
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}
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static int rt2800pci_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
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{
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struct rt2x00_dev *rt2x00dev = hw->priv;
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u32 reg;
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bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
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rt2800_register_read(rt2x00dev, TX_RTS_CFG, ®);
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rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, value);
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rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
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rt2800_register_read(rt2x00dev, CCK_PROT_CFG, ®);
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rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, enabled);
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rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
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rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®);
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rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, enabled);
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rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
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rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®);
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rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, enabled);
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rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
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rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®);
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rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, enabled);
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rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
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rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®);
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rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, enabled);
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rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
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rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®);
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rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, enabled);
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rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
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return 0;
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}
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static int rt2800pci_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
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const struct ieee80211_tx_queue_params *params)
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{
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struct rt2x00_dev *rt2x00dev = hw->priv;
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struct data_queue *queue;
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struct rt2x00_field32 field;
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int retval;
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u32 reg;
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u32 offset;
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/*
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* First pass the configuration through rt2x00lib, that will
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* update the queue settings and validate the input. After that
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* we are free to update the registers based on the value
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* in the queue parameter.
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*/
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retval = rt2x00mac_conf_tx(hw, queue_idx, params);
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if (retval)
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return retval;
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/*
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* We only need to perform additional register initialization
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* for WMM queues/
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*/
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if (queue_idx >= 4)
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return 0;
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queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
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/* Update WMM TXOP register */
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offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
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field.bit_offset = (queue_idx & 1) * 16;
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field.bit_mask = 0xffff << field.bit_offset;
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rt2800_register_read(rt2x00dev, offset, ®);
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rt2x00_set_field32(®, field, queue->txop);
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rt2800_register_write(rt2x00dev, offset, reg);
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/* Update WMM registers */
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field.bit_offset = queue_idx * 4;
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field.bit_mask = 0xf << field.bit_offset;
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rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, ®);
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rt2x00_set_field32(®, field, queue->aifs);
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rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
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rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, ®);
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rt2x00_set_field32(®, field, queue->cw_min);
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rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
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rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, ®);
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rt2x00_set_field32(®, field, queue->cw_max);
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rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
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/* Update EDCA registers */
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offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
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rt2800_register_read(rt2x00dev, offset, ®);
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rt2x00_set_field32(®, EDCA_AC0_CFG_TX_OP, queue->txop);
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rt2x00_set_field32(®, EDCA_AC0_CFG_AIFSN, queue->aifs);
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rt2x00_set_field32(®, EDCA_AC0_CFG_CWMIN, queue->cw_min);
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rt2x00_set_field32(®, EDCA_AC0_CFG_CWMAX, queue->cw_max);
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rt2800_register_write(rt2x00dev, offset, reg);
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return 0;
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}
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static u64 rt2800pci_get_tsf(struct ieee80211_hw *hw)
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{
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struct rt2x00_dev *rt2x00dev = hw->priv;
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u64 tsf;
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u32 reg;
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rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, ®);
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tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
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rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, ®);
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tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
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return tsf;
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}
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static const struct ieee80211_ops rt2800pci_mac80211_ops = {
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.tx = rt2x00mac_tx,
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.start = rt2x00mac_start,
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.stop = rt2x00mac_stop,
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.add_interface = rt2x00mac_add_interface,
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.remove_interface = rt2x00mac_remove_interface,
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.config = rt2x00mac_config,
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.configure_filter = rt2x00mac_configure_filter,
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.set_key = rt2x00mac_set_key,
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.get_stats = rt2x00mac_get_stats,
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.get_tkip_seq = rt2800pci_get_tkip_seq,
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.set_rts_threshold = rt2800pci_set_rts_threshold,
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.bss_info_changed = rt2x00mac_bss_info_changed,
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.conf_tx = rt2800pci_conf_tx,
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.get_tx_stats = rt2x00mac_get_tx_stats,
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.get_tsf = rt2800pci_get_tsf,
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.rfkill_poll = rt2x00mac_rfkill_poll,
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};
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static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
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.irq_handler = rt2800pci_interrupt,
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.probe_hw = rt2800pci_probe_hw,
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@ -1730,7 +1575,7 @@ static const struct rt2x00_ops rt2800pci_ops = {
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.tx = &rt2800pci_queue_tx,
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.bcn = &rt2800pci_queue_bcn,
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.lib = &rt2800pci_rt2x00_ops,
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.hw = &rt2800pci_mac80211_ops,
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.hw = &rt2800_mac80211_ops,
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#ifdef CONFIG_RT2X00_LIB_DEBUGFS
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.debugfs = &rt2800_rt2x00debug,
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#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
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@ -1119,162 +1119,6 @@ static int rt2800usb_probe_hw(struct rt2x00_dev *rt2x00dev)
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return 0;
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}
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/*
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* IEEE80211 stack callback functions.
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*/
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static void rt2800usb_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx,
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u32 *iv32, u16 *iv16)
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{
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struct rt2x00_dev *rt2x00dev = hw->priv;
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struct mac_iveiv_entry iveiv_entry;
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u32 offset;
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offset = MAC_IVEIV_ENTRY(hw_key_idx);
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rt2800_register_multiread(rt2x00dev, offset,
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&iveiv_entry, sizeof(iveiv_entry));
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memcpy(&iveiv_entry.iv[0], iv16, sizeof(iv16));
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memcpy(&iveiv_entry.iv[4], iv32, sizeof(iv32));
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}
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static int rt2800usb_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
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{
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struct rt2x00_dev *rt2x00dev = hw->priv;
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u32 reg;
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bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
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rt2800_register_read(rt2x00dev, TX_RTS_CFG, ®);
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rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, value);
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rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
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rt2800_register_read(rt2x00dev, CCK_PROT_CFG, ®);
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rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, enabled);
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rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
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rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®);
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||||
rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, enabled);
|
||||
rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
|
||||
|
||||
rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®);
|
||||
rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, enabled);
|
||||
rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
|
||||
|
||||
rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®);
|
||||
rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, enabled);
|
||||
rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
|
||||
|
||||
rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®);
|
||||
rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, enabled);
|
||||
rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
|
||||
|
||||
rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®);
|
||||
rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, enabled);
|
||||
rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int rt2800usb_conf_tx(struct ieee80211_hw *hw, u16 queue_idx,
|
||||
const struct ieee80211_tx_queue_params *params)
|
||||
{
|
||||
struct rt2x00_dev *rt2x00dev = hw->priv;
|
||||
struct data_queue *queue;
|
||||
struct rt2x00_field32 field;
|
||||
int retval;
|
||||
u32 reg;
|
||||
u32 offset;
|
||||
|
||||
/*
|
||||
* First pass the configuration through rt2x00lib, that will
|
||||
* update the queue settings and validate the input. After that
|
||||
* we are free to update the registers based on the value
|
||||
* in the queue parameter.
|
||||
*/
|
||||
retval = rt2x00mac_conf_tx(hw, queue_idx, params);
|
||||
if (retval)
|
||||
return retval;
|
||||
|
||||
/*
|
||||
* We only need to perform additional register initialization
|
||||
* for WMM queues/
|
||||
*/
|
||||
if (queue_idx >= 4)
|
||||
return 0;
|
||||
|
||||
queue = rt2x00queue_get_queue(rt2x00dev, queue_idx);
|
||||
|
||||
/* Update WMM TXOP register */
|
||||
offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
|
||||
field.bit_offset = (queue_idx & 1) * 16;
|
||||
field.bit_mask = 0xffff << field.bit_offset;
|
||||
|
||||
rt2800_register_read(rt2x00dev, offset, ®);
|
||||
rt2x00_set_field32(®, field, queue->txop);
|
||||
rt2800_register_write(rt2x00dev, offset, reg);
|
||||
|
||||
/* Update WMM registers */
|
||||
field.bit_offset = queue_idx * 4;
|
||||
field.bit_mask = 0xf << field.bit_offset;
|
||||
|
||||
rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, ®);
|
||||
rt2x00_set_field32(®, field, queue->aifs);
|
||||
rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
|
||||
|
||||
rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, ®);
|
||||
rt2x00_set_field32(®, field, queue->cw_min);
|
||||
rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
|
||||
|
||||
rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, ®);
|
||||
rt2x00_set_field32(®, field, queue->cw_max);
|
||||
rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
|
||||
|
||||
/* Update EDCA registers */
|
||||
offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
|
||||
|
||||
rt2800_register_read(rt2x00dev, offset, ®);
|
||||
rt2x00_set_field32(®, EDCA_AC0_CFG_TX_OP, queue->txop);
|
||||
rt2x00_set_field32(®, EDCA_AC0_CFG_AIFSN, queue->aifs);
|
||||
rt2x00_set_field32(®, EDCA_AC0_CFG_CWMIN, queue->cw_min);
|
||||
rt2x00_set_field32(®, EDCA_AC0_CFG_CWMAX, queue->cw_max);
|
||||
rt2800_register_write(rt2x00dev, offset, reg);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static u64 rt2800usb_get_tsf(struct ieee80211_hw *hw)
|
||||
{
|
||||
struct rt2x00_dev *rt2x00dev = hw->priv;
|
||||
u64 tsf;
|
||||
u32 reg;
|
||||
|
||||
rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, ®);
|
||||
tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
|
||||
rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, ®);
|
||||
tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
|
||||
|
||||
return tsf;
|
||||
}
|
||||
|
||||
static const struct ieee80211_ops rt2800usb_mac80211_ops = {
|
||||
.tx = rt2x00mac_tx,
|
||||
.start = rt2x00mac_start,
|
||||
.stop = rt2x00mac_stop,
|
||||
.add_interface = rt2x00mac_add_interface,
|
||||
.remove_interface = rt2x00mac_remove_interface,
|
||||
.config = rt2x00mac_config,
|
||||
.configure_filter = rt2x00mac_configure_filter,
|
||||
.set_tim = rt2x00mac_set_tim,
|
||||
.set_key = rt2x00mac_set_key,
|
||||
.get_stats = rt2x00mac_get_stats,
|
||||
.get_tkip_seq = rt2800usb_get_tkip_seq,
|
||||
.set_rts_threshold = rt2800usb_set_rts_threshold,
|
||||
.bss_info_changed = rt2x00mac_bss_info_changed,
|
||||
.conf_tx = rt2800usb_conf_tx,
|
||||
.get_tx_stats = rt2x00mac_get_tx_stats,
|
||||
.get_tsf = rt2800usb_get_tsf,
|
||||
.rfkill_poll = rt2x00mac_rfkill_poll,
|
||||
};
|
||||
|
||||
static const struct rt2x00lib_ops rt2800usb_rt2x00_ops = {
|
||||
.probe_hw = rt2800usb_probe_hw,
|
||||
.get_firmware_name = rt2800usb_get_firmware_name,
|
||||
@ -1336,7 +1180,7 @@ static const struct rt2x00_ops rt2800usb_ops = {
|
||||
.tx = &rt2800usb_queue_tx,
|
||||
.bcn = &rt2800usb_queue_bcn,
|
||||
.lib = &rt2800usb_rt2x00_ops,
|
||||
.hw = &rt2800usb_mac80211_ops,
|
||||
.hw = &rt2800_mac80211_ops,
|
||||
#ifdef CONFIG_RT2X00_LIB_DEBUGFS
|
||||
.debugfs = &rt2800_rt2x00debug,
|
||||
#endif /* CONFIG_RT2X00_LIB_DEBUGFS */
|
||||
|
Loading…
Reference in New Issue
Block a user