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soc/fsl/qe: round brg_freq to 1kHz granularity

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Because of integer computation rounding in u-boot (that sets the QE
brg-frequency DTS prop), the clk value is 99999999 Hz even though it is
100 MHz.

When setting brg clks that are exact divisors of 100 MHz, this small
differnce plays a role and can result in lower clks to be output (for
instance 20 MHz - divide by 5 - results in 16.666 MHz - divide by 6).

This patch fixes that by "forcing" the brg_clk to the nearest kHz when
the difference is below 2 integer rounding errors (i.e. 4).

Signed-off-by: Valentin Longchamp <valentin.longchamp@keymile.com>
Signed-off-by: Scott Wood <oss@buserror.net>
This commit is contained in:
Valentin Longchamp 2017-02-17 11:29:45 +01:00 committed by Scott Wood
parent b54ea82f01
commit 2ccf80b756
1 changed files with 13 additions and 0 deletions
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13
drivers/soc/fsl/qe/qe.c
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@ -161,11 +161,15 @@ EXPORT_SYMBOL(qe_issue_cmd);
*/
static unsigned int brg_clk = 0;
#define CLK_GRAN (1000)
#define CLK_GRAN_LIMIT (5)
unsigned int qe_get_brg_clk(void)
{
struct device_node *qe;
int size;
const u32 *prop;
unsigned int mod;
if (brg_clk)
return brg_clk;
@ -183,6 +187,15 @@ unsigned int qe_get_brg_clk(void)
of_node_put(qe);
/* round this if near to a multiple of CLK_GRAN */
mod = brg_clk % CLK_GRAN;
if (mod) {
if (mod < CLK_GRAN_LIMIT)
brg_clk -= mod;
else if (mod > (CLK_GRAN - CLK_GRAN_LIMIT))
brg_clk += CLK_GRAN - mod;
}
return brg_clk;
}
EXPORT_SYMBOL(qe_get_brg_clk);