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dt-bindings: clock: Add A7 PLL binding for SDX65

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Add information for Cortex A7 PLL clock in Qualcomm
platform SDX65.

Signed-off-by: Rohit Agarwal <quic_rohiagar@quicinc.com>
Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lore.kernel.org/r/1645505785-2271-2-git-send-email-quic_rohiagar@quicinc.com
This commit is contained in:
Rohit Agarwal 2022-02-22 10:26:21 +05:30 committed by Bjorn Andersson
parent 013804a727
commit 2cabc45237
1 changed files with 1 additions and 1 deletions
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2
Documentation/devicetree/bindings/clock/qcom,a7pll.yaml
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@ -10,7 +10,7 @@ maintainers:
- Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
description:
The A7 PLL on the Qualcomm platforms like SDX55 is used to provide high
The A7 PLL on the Qualcomm platforms like SDX55, SDX65 is used to provide high
frequency clock to the CPU.
properties: