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net/mlx5: HWS, added send engine and context handling
Added implementation of send engine and handling of HWS context. Reviewed-by: Itamar Gozlan <igozlan@nvidia.com> Signed-off-by: Yevgeny Kliteynik <kliteyn@nvidia.com> Signed-off-by: Saeed Mahameed <saeedm@nvidia.com>
This commit is contained in:
Yevgeny Kliteynik
Saeed Mahameed
parent
d4a605e968
commit
2ca62599aa
@ -0,0 +1,260 @@
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// SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB
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/* Copyright (c) 2024 NVIDIA CORPORATION. All rights reserved. */
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#include "mlx5hws_internal.h"
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bool mlx5hws_context_cap_dynamic_reparse(struct mlx5hws_context *ctx)
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{
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return IS_BIT_SET(ctx->caps->rtc_reparse_mode, MLX5_IFC_RTC_REPARSE_BY_STC);
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}
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u8 mlx5hws_context_get_reparse_mode(struct mlx5hws_context *ctx)
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{
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/* Prefer to use dynamic reparse, reparse only specific actions */
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if (mlx5hws_context_cap_dynamic_reparse(ctx))
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return MLX5_IFC_RTC_REPARSE_NEVER;
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/* Otherwise use less efficient static */
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return MLX5_IFC_RTC_REPARSE_ALWAYS;
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}
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static int hws_context_pools_init(struct mlx5hws_context *ctx)
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{
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struct mlx5hws_pool_attr pool_attr = {0};
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u8 max_log_sz;
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int ret;
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int i;
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ret = mlx5hws_pat_init_pattern_cache(&ctx->pattern_cache);
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if (ret)
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return ret;
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ret = mlx5hws_definer_init_cache(&ctx->definer_cache);
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if (ret)
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goto uninit_pat_cache;
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/* Create an STC pool per FT type */
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pool_attr.pool_type = MLX5HWS_POOL_TYPE_STC;
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pool_attr.flags = MLX5HWS_POOL_FLAGS_FOR_STC_POOL;
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max_log_sz = min(MLX5HWS_POOL_STC_LOG_SZ, ctx->caps->stc_alloc_log_max);
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pool_attr.alloc_log_sz = max(max_log_sz, ctx->caps->stc_alloc_log_gran);
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for (i = 0; i < MLX5HWS_TABLE_TYPE_MAX; i++) {
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pool_attr.table_type = i;
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ctx->stc_pool[i] = mlx5hws_pool_create(ctx, &pool_attr);
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if (!ctx->stc_pool[i]) {
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mlx5hws_err(ctx, "Failed to allocate STC pool [%d]", i);
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ret = -ENOMEM;
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goto free_stc_pools;
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}
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}
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return 0;
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free_stc_pools:
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for (i = 0; i < MLX5HWS_TABLE_TYPE_MAX; i++)
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if (ctx->stc_pool[i])
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mlx5hws_pool_destroy(ctx->stc_pool[i]);
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mlx5hws_definer_uninit_cache(ctx->definer_cache);
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uninit_pat_cache:
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mlx5hws_pat_uninit_pattern_cache(ctx->pattern_cache);
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return ret;
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}
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static void hws_context_pools_uninit(struct mlx5hws_context *ctx)
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{
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int i;
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for (i = 0; i < MLX5HWS_TABLE_TYPE_MAX; i++) {
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if (ctx->stc_pool[i])
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mlx5hws_pool_destroy(ctx->stc_pool[i]);
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}
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mlx5hws_definer_uninit_cache(ctx->definer_cache);
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mlx5hws_pat_uninit_pattern_cache(ctx->pattern_cache);
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}
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static int hws_context_init_pd(struct mlx5hws_context *ctx)
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{
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int ret = 0;
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ret = mlx5_core_alloc_pd(ctx->mdev, &ctx->pd_num);
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if (ret) {
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mlx5hws_err(ctx, "Failed to allocate PD\n");
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return ret;
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}
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ctx->flags |= MLX5HWS_CONTEXT_FLAG_PRIVATE_PD;
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return 0;
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}
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static int hws_context_uninit_pd(struct mlx5hws_context *ctx)
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{
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if (ctx->flags & MLX5HWS_CONTEXT_FLAG_PRIVATE_PD)
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mlx5_core_dealloc_pd(ctx->mdev, ctx->pd_num);
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return 0;
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}
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static void hws_context_check_hws_supp(struct mlx5hws_context *ctx)
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{
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struct mlx5hws_cmd_query_caps *caps = ctx->caps;
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/* HWS not supported on device / FW */
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if (!caps->wqe_based_update) {
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mlx5hws_err(ctx, "Required HWS WQE based insertion cap not supported\n");
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return;
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}
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if (!caps->eswitch_manager) {
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mlx5hws_err(ctx, "HWS is not supported for non eswitch manager port\n");
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return;
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}
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/* Current solution requires all rules to set reparse bit */
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if ((!caps->nic_ft.reparse ||
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(!caps->fdb_ft.reparse && caps->eswitch_manager)) ||
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!IS_BIT_SET(caps->rtc_reparse_mode, MLX5_IFC_RTC_REPARSE_ALWAYS)) {
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mlx5hws_err(ctx, "Required HWS reparse cap not supported\n");
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return;
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}
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/* FW/HW must support 8DW STE */
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if (!IS_BIT_SET(caps->ste_format, MLX5_IFC_RTC_STE_FORMAT_8DW)) {
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mlx5hws_err(ctx, "Required HWS STE format not supported\n");
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return;
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}
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/* Adding rules by hash and by offset are requirements */
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if (!IS_BIT_SET(caps->rtc_index_mode, MLX5_IFC_RTC_STE_UPDATE_MODE_BY_HASH) ||
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!IS_BIT_SET(caps->rtc_index_mode, MLX5_IFC_RTC_STE_UPDATE_MODE_BY_OFFSET)) {
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mlx5hws_err(ctx, "Required HWS RTC update mode not supported\n");
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return;
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}
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/* Support for SELECT definer ID is required */
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if (!IS_BIT_SET(caps->definer_format_sup, MLX5_IFC_DEFINER_FORMAT_ID_SELECT)) {
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mlx5hws_err(ctx, "Required HWS Dynamic definer not supported\n");
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return;
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}
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ctx->flags |= MLX5HWS_CONTEXT_FLAG_HWS_SUPPORT;
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}
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static int hws_context_init_hws(struct mlx5hws_context *ctx,
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struct mlx5hws_context_attr *attr)
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{
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int ret;
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hws_context_check_hws_supp(ctx);
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if (!(ctx->flags & MLX5HWS_CONTEXT_FLAG_HWS_SUPPORT))
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return 0;
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ret = hws_context_init_pd(ctx);
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if (ret)
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return ret;
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ret = hws_context_pools_init(ctx);
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if (ret)
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goto uninit_pd;
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if (attr->bwc)
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ctx->flags |= MLX5HWS_CONTEXT_FLAG_BWC_SUPPORT;
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ret = mlx5hws_send_queues_open(ctx, attr->queues, attr->queue_size);
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if (ret)
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goto pools_uninit;
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INIT_LIST_HEAD(&ctx->tbl_list);
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return 0;
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pools_uninit:
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hws_context_pools_uninit(ctx);
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uninit_pd:
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hws_context_uninit_pd(ctx);
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return ret;
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}
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static void hws_context_uninit_hws(struct mlx5hws_context *ctx)
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{
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if (!(ctx->flags & MLX5HWS_CONTEXT_FLAG_HWS_SUPPORT))
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return;
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mlx5hws_send_queues_close(ctx);
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hws_context_pools_uninit(ctx);
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hws_context_uninit_pd(ctx);
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}
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struct mlx5hws_context *mlx5hws_context_open(struct mlx5_core_dev *mdev,
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struct mlx5hws_context_attr *attr)
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{
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struct mlx5hws_context *ctx;
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int ret;
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ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
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if (!ctx)
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return NULL;
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ctx->mdev = mdev;
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mutex_init(&ctx->ctrl_lock);
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xa_init(&ctx->peer_ctx_xa);
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ctx->caps = kzalloc(sizeof(*ctx->caps), GFP_KERNEL);
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if (!ctx->caps)
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goto free_ctx;
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ret = mlx5hws_cmd_query_caps(mdev, ctx->caps);
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if (ret)
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goto free_caps;
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ret = mlx5hws_vport_init_vports(ctx);
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if (ret)
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goto free_caps;
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ret = hws_context_init_hws(ctx, attr);
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if (ret)
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goto uninit_vports;
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mlx5hws_debug_init_dump(ctx);
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return ctx;
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uninit_vports:
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mlx5hws_vport_uninit_vports(ctx);
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free_caps:
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kfree(ctx->caps);
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free_ctx:
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xa_destroy(&ctx->peer_ctx_xa);
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mutex_destroy(&ctx->ctrl_lock);
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kfree(ctx);
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return NULL;
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}
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int mlx5hws_context_close(struct mlx5hws_context *ctx)
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{
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mlx5hws_debug_uninit_dump(ctx);
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hws_context_uninit_hws(ctx);
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mlx5hws_vport_uninit_vports(ctx);
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kfree(ctx->caps);
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xa_destroy(&ctx->peer_ctx_xa);
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mutex_destroy(&ctx->ctrl_lock);
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kfree(ctx);
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return 0;
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}
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void mlx5hws_context_set_peer(struct mlx5hws_context *ctx,
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struct mlx5hws_context *peer_ctx,
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u16 peer_vhca_id)
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{
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mutex_lock(&ctx->ctrl_lock);
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if (xa_err(xa_store(&ctx->peer_ctx_xa, peer_vhca_id, peer_ctx, GFP_KERNEL)))
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pr_warn("HWS: failed storing peer vhca ID in peer xarray\n");
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mutex_unlock(&ctx->ctrl_lock);
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}
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@ -0,0 +1,64 @@
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/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
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/* Copyright (c) 2024 NVIDIA Corporation & Affiliates */
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#ifndef MLX5HWS_CONTEXT_H_
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#define MLX5HWS_CONTEXT_H_
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enum mlx5hws_context_flags {
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MLX5HWS_CONTEXT_FLAG_HWS_SUPPORT = 1 << 0,
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MLX5HWS_CONTEXT_FLAG_PRIVATE_PD = 1 << 1,
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MLX5HWS_CONTEXT_FLAG_BWC_SUPPORT = 1 << 2,
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};
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enum mlx5hws_context_shared_stc_type {
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MLX5HWS_CONTEXT_SHARED_STC_DECAP_L3 = 0,
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MLX5HWS_CONTEXT_SHARED_STC_DOUBLE_POP = 1,
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MLX5HWS_CONTEXT_SHARED_STC_MAX = 2,
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};
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struct mlx5hws_context_common_res {
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struct mlx5hws_action_default_stc *default_stc;
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struct mlx5hws_action_shared_stc *shared_stc[MLX5HWS_CONTEXT_SHARED_STC_MAX];
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struct mlx5hws_cmd_forward_tbl *default_miss;
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};
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struct mlx5hws_context_debug_info {
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struct dentry *steering_debugfs;
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struct dentry *fdb_debugfs;
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};
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struct mlx5hws_context_vports {
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u16 esw_manager_gvmi;
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u16 uplink_gvmi;
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struct xarray vport_gvmi_xa;
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};
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struct mlx5hws_context {
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struct mlx5_core_dev *mdev;
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struct mlx5hws_cmd_query_caps *caps;
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u32 pd_num;
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struct mlx5hws_pool *stc_pool[MLX5HWS_TABLE_TYPE_MAX];
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struct mlx5hws_context_common_res common_res[MLX5HWS_TABLE_TYPE_MAX];
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struct mlx5hws_pattern_cache *pattern_cache;
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struct mlx5hws_definer_cache *definer_cache;
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struct mutex ctrl_lock; /* control lock to protect the whole context */
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enum mlx5hws_context_flags flags;
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struct mlx5hws_send_engine *send_queue;
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size_t queues;
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struct mutex *bwc_send_queue_locks; /* protect BWC queues */
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struct list_head tbl_list;
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struct mlx5hws_context_debug_info debug_info;
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struct xarray peer_ctx_xa;
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struct mlx5hws_context_vports vports;
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};
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static inline bool mlx5hws_context_bwc_supported(struct mlx5hws_context *ctx)
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{
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return ctx->flags & MLX5HWS_CONTEXT_FLAG_BWC_SUPPORT;
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}
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bool mlx5hws_context_cap_dynamic_reparse(struct mlx5hws_context *ctx);
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u8 mlx5hws_context_get_reparse_mode(struct mlx5hws_context *ctx);
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#endif /* MLX5HWS_CONTEXT_H_ */
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1209
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws_send.c
Normal file
1209
drivers/net/ethernet/mellanox/mlx5/core/steering/hws/mlx5hws_send.c
Normal file
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,270 @@
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/* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
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/* Copyright (c) 2024 NVIDIA Corporation & Affiliates */
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#ifndef MLX5HWS_SEND_H_
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#define MLX5HWS_SEND_H_
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/* As a single operation requires at least two WQEBBS.
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* This means a maximum of 16 such operations per rule.
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*/
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#define MAX_WQES_PER_RULE 32
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enum mlx5hws_wqe_opcode {
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MLX5HWS_WQE_OPCODE_TBL_ACCESS = 0x2c,
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};
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enum mlx5hws_wqe_opmod {
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MLX5HWS_WQE_OPMOD_GTA_STE = 0,
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MLX5HWS_WQE_OPMOD_GTA_MOD_ARG = 1,
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};
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enum mlx5hws_wqe_gta_opcode {
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MLX5HWS_WQE_GTA_OP_ACTIVATE = 0,
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MLX5HWS_WQE_GTA_OP_DEACTIVATE = 1,
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};
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enum mlx5hws_wqe_gta_opmod {
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MLX5HWS_WQE_GTA_OPMOD_STE = 0,
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MLX5HWS_WQE_GTA_OPMOD_MOD_ARG = 1,
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};
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enum mlx5hws_wqe_gta_sz {
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MLX5HWS_WQE_SZ_GTA_CTRL = 48,
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MLX5HWS_WQE_SZ_GTA_DATA = 64,
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};
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/* WQE Control segment. */
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struct mlx5hws_wqe_ctrl_seg {
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__be32 opmod_idx_opcode;
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__be32 qpn_ds;
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__be32 flags;
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__be32 imm;
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};
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struct mlx5hws_wqe_gta_ctrl_seg {
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__be32 op_dirix;
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__be32 stc_ix[5];
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__be32 rsvd0[6];
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};
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struct mlx5hws_wqe_gta_data_seg_ste {
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__be32 rsvd0_ctr_id;
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__be32 rsvd1_definer;
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__be32 rsvd2[3];
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union {
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struct {
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__be32 action[3];
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__be32 tag[8];
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};
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__be32 jumbo[11];
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};
|
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};
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struct mlx5hws_wqe_gta_data_seg_arg {
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__be32 action_args[8];
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};
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struct mlx5hws_wqe_gta {
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struct mlx5hws_wqe_gta_ctrl_seg gta_ctrl;
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union {
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struct mlx5hws_wqe_gta_data_seg_ste seg_ste;
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struct mlx5hws_wqe_gta_data_seg_arg seg_arg;
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};
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};
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struct mlx5hws_send_ring_cq {
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struct mlx5_core_dev *mdev;
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struct mlx5_cqwq wq;
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struct mlx5_wq_ctrl wq_ctrl;
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struct mlx5_core_cq mcq;
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u16 poll_wqe;
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};
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struct mlx5hws_send_ring_priv {
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struct mlx5hws_rule *rule;
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void *user_data;
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u32 num_wqebbs;
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u32 id;
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u32 retry_id;
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u32 *used_id;
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};
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struct mlx5hws_send_ring_dep_wqe {
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struct mlx5hws_wqe_gta_ctrl_seg wqe_ctrl;
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struct mlx5hws_wqe_gta_data_seg_ste wqe_data;
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struct mlx5hws_rule *rule;
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u32 rtc_0;
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u32 rtc_1;
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u32 retry_rtc_0;
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u32 retry_rtc_1;
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u32 direct_index;
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void *user_data;
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};
|
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|
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struct mlx5hws_send_ring_sq {
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struct mlx5_core_dev *mdev;
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u16 cur_post;
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u16 buf_mask;
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struct mlx5hws_send_ring_priv *wr_priv;
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unsigned int last_idx;
|
||||
struct mlx5hws_send_ring_dep_wqe *dep_wqe;
|
||||
unsigned int head_dep_idx;
|
||||
unsigned int tail_dep_idx;
|
||||
u32 sqn;
|
||||
struct mlx5_wq_cyc wq;
|
||||
struct mlx5_wq_ctrl wq_ctrl;
|
||||
void __iomem *uar_map;
|
||||
};
|
||||
|
||||
struct mlx5hws_send_ring {
|
||||
struct mlx5hws_send_ring_cq send_cq;
|
||||
struct mlx5hws_send_ring_sq send_sq;
|
||||
};
|
||||
|
||||
struct mlx5hws_completed_poll_entry {
|
||||
void *user_data;
|
||||
enum mlx5hws_flow_op_status status;
|
||||
};
|
||||
|
||||
struct mlx5hws_completed_poll {
|
||||
struct mlx5hws_completed_poll_entry *entries;
|
||||
u16 ci;
|
||||
u16 pi;
|
||||
u16 mask;
|
||||
};
|
||||
|
||||
struct mlx5hws_send_engine {
|
||||
struct mlx5hws_send_ring send_ring;
|
||||
struct mlx5_uars_page *uar; /* Uar is shared between rings of a queue */
|
||||
struct mlx5hws_completed_poll completed;
|
||||
u16 used_entries;
|
||||
u16 num_entries;
|
||||
bool err;
|
||||
struct mutex lock; /* Protects the send engine */
|
||||
};
|
||||
|
||||
struct mlx5hws_send_engine_post_ctrl {
|
||||
struct mlx5hws_send_engine *queue;
|
||||
struct mlx5hws_send_ring *send_ring;
|
||||
size_t num_wqebbs;
|
||||
};
|
||||
|
||||
struct mlx5hws_send_engine_post_attr {
|
||||
u8 opcode;
|
||||
u8 opmod;
|
||||
u8 notify_hw;
|
||||
u8 fence;
|
||||
u8 match_definer_id;
|
||||
u8 range_definer_id;
|
||||
size_t len;
|
||||
struct mlx5hws_rule *rule;
|
||||
u32 id;
|
||||
u32 retry_id;
|
||||
u32 *used_id;
|
||||
void *user_data;
|
||||
};
|
||||
|
||||
struct mlx5hws_send_ste_attr {
|
||||
u32 rtc_0;
|
||||
u32 rtc_1;
|
||||
u32 retry_rtc_0;
|
||||
u32 retry_rtc_1;
|
||||
u32 *used_id_rtc_0;
|
||||
u32 *used_id_rtc_1;
|
||||
bool wqe_tag_is_jumbo;
|
||||
u8 gta_opcode;
|
||||
u32 direct_index;
|
||||
struct mlx5hws_send_engine_post_attr send_attr;
|
||||
struct mlx5hws_rule_match_tag *wqe_tag;
|
||||
struct mlx5hws_rule_match_tag *range_wqe_tag;
|
||||
struct mlx5hws_wqe_gta_ctrl_seg *wqe_ctrl;
|
||||
struct mlx5hws_wqe_gta_data_seg_ste *wqe_data;
|
||||
struct mlx5hws_wqe_gta_data_seg_ste *range_wqe_data;
|
||||
};
|
||||
|
||||
struct mlx5hws_send_ring_dep_wqe *
|
||||
mlx5hws_send_add_new_dep_wqe(struct mlx5hws_send_engine *queue);
|
||||
|
||||
void mlx5hws_send_abort_new_dep_wqe(struct mlx5hws_send_engine *queue);
|
||||
|
||||
void mlx5hws_send_all_dep_wqe(struct mlx5hws_send_engine *queue);
|
||||
|
||||
void mlx5hws_send_queue_close(struct mlx5hws_send_engine *queue);
|
||||
|
||||
int mlx5hws_send_queue_open(struct mlx5hws_context *ctx,
|
||||
struct mlx5hws_send_engine *queue,
|
||||
u16 queue_size);
|
||||
|
||||
void mlx5hws_send_queues_close(struct mlx5hws_context *ctx);
|
||||
|
||||
int mlx5hws_send_queues_open(struct mlx5hws_context *ctx,
|
||||
u16 queues,
|
||||
u16 queue_size);
|
||||
|
||||
int mlx5hws_send_queue_action(struct mlx5hws_context *ctx,
|
||||
u16 queue_id,
|
||||
u32 actions);
|
||||
|
||||
int mlx5hws_send_test(struct mlx5hws_context *ctx,
|
||||
u16 queues,
|
||||
u16 queue_size);
|
||||
|
||||
struct mlx5hws_send_engine_post_ctrl
|
||||
mlx5hws_send_engine_post_start(struct mlx5hws_send_engine *queue);
|
||||
|
||||
void mlx5hws_send_engine_post_req_wqe(struct mlx5hws_send_engine_post_ctrl *ctrl,
|
||||
char **buf, size_t *len);
|
||||
|
||||
void mlx5hws_send_engine_post_end(struct mlx5hws_send_engine_post_ctrl *ctrl,
|
||||
struct mlx5hws_send_engine_post_attr *attr);
|
||||
|
||||
void mlx5hws_send_ste(struct mlx5hws_send_engine *queue,
|
||||
struct mlx5hws_send_ste_attr *ste_attr);
|
||||
|
||||
void mlx5hws_send_stes_fw(struct mlx5hws_context *ctx,
|
||||
struct mlx5hws_send_engine *queue,
|
||||
struct mlx5hws_send_ste_attr *ste_attr);
|
||||
|
||||
void mlx5hws_send_engine_flush_queue(struct mlx5hws_send_engine *queue);
|
||||
|
||||
static inline bool mlx5hws_send_engine_empty(struct mlx5hws_send_engine *queue)
|
||||
{
|
||||
struct mlx5hws_send_ring_sq *send_sq = &queue->send_ring.send_sq;
|
||||
struct mlx5hws_send_ring_cq *send_cq = &queue->send_ring.send_cq;
|
||||
|
||||
return ((send_sq->cur_post & send_sq->buf_mask) == send_cq->poll_wqe);
|
||||
}
|
||||
|
||||
static inline bool mlx5hws_send_engine_full(struct mlx5hws_send_engine *queue)
|
||||
{
|
||||
return queue->used_entries >= queue->num_entries;
|
||||
}
|
||||
|
||||
static inline void mlx5hws_send_engine_inc_rule(struct mlx5hws_send_engine *queue)
|
||||
{
|
||||
queue->used_entries++;
|
||||
}
|
||||
|
||||
static inline void mlx5hws_send_engine_dec_rule(struct mlx5hws_send_engine *queue)
|
||||
{
|
||||
queue->used_entries--;
|
||||
}
|
||||
|
||||
static inline void mlx5hws_send_engine_gen_comp(struct mlx5hws_send_engine *queue,
|
||||
void *user_data,
|
||||
int comp_status)
|
||||
{
|
||||
struct mlx5hws_completed_poll *comp = &queue->completed;
|
||||
|
||||
comp->entries[comp->pi].status = comp_status;
|
||||
comp->entries[comp->pi].user_data = user_data;
|
||||
|
||||
comp->pi = (comp->pi + 1) & comp->mask;
|
||||
}
|
||||
|
||||
static inline bool mlx5hws_send_engine_err(struct mlx5hws_send_engine *queue)
|
||||
{
|
||||
return queue->err;
|
||||
}
|
||||
|
||||
#endif /* MLX5HWS_SEND_H_ */
|
||||
Loading…
Reference in New Issue
Block a user