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[IA64] implement ticket locks for Itanium
Back in January 2008 Nick Piggin implemented "ticket" spinlocks
for X86 (See commit 314cdbefd1).
IA64 implementation has a couple of differences because of the
available atomic operations ... e.g. we have no fetchadd2 instruction
that operates on a 16-bit quantity so we make ticket locks use
a 32-bit word for each of the current ticket and now-serving values.
Performance on uncontended locks is about 8% worse than the previous
implementation, but this seems a good trade for determinism in the
contended case. Performance impact on macro-level benchmarks is in
the noise.
Signed-off-by: Tony Luck <tony.luck@intel.com>
This commit is contained in:
Tony Luck
parent
53cddfcc0e
commit
2c86963b09
@ -60,9 +60,7 @@ config IOMMU_HELPER
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bool
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config GENERIC_LOCKBREAK
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bool
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default y
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depends on SMP && PREEMPT
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def_bool n
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config RWSEM_XCHGADD_ALGORITHM
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bool
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@ -19,103 +19,106 @@
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#define __raw_spin_lock_init(x) ((x)->lock = 0)
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#ifdef ASM_SUPPORTED
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/*
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* Try to get the lock. If we fail to get the lock, make a non-standard call to
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* ia64_spinlock_contention(). We do not use a normal call because that would force all
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* callers of __raw_spin_lock() to be non-leaf routines. Instead, ia64_spinlock_contention() is
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* carefully coded to touch only those registers that __raw_spin_lock() marks "clobbered".
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* Ticket locks are conceptually two parts, one indicating the current head of
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* the queue, and the other indicating the current tail. The lock is acquired
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* by atomically noting the tail and incrementing it by one (thus adding
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* ourself to the queue and noting our position), then waiting until the head
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* becomes equal to the the initial value of the tail.
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*
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* 63 32 31 0
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* +----------------------------------------------------+
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* | next_ticket_number | now_serving |
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* +----------------------------------------------------+
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*/
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#define IA64_SPINLOCK_CLOBBERS "ar.ccv", "ar.pfs", "p14", "p15", "r27", "r28", "r29", "r30", "b6", "memory"
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#define TICKET_SHIFT 32
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static inline void
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__raw_spin_lock_flags (raw_spinlock_t *lock, unsigned long flags)
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static __always_inline void __ticket_spin_lock(raw_spinlock_t *lock)
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{
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register volatile unsigned int *ptr asm ("r31") = &lock->lock;
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int *p = (int *)&lock->lock, turn, now_serving;
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#if (__GNUC__ == 3 && __GNUC_MINOR__ < 3)
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# ifdef CONFIG_ITANIUM
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/* don't use brl on Itanium... */
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asm volatile ("{\n\t"
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" mov ar.ccv = r0\n\t"
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" mov r28 = ip\n\t"
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" mov r30 = 1;;\n\t"
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"}\n\t"
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"cmpxchg4.acq r30 = [%1], r30, ar.ccv\n\t"
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"movl r29 = ia64_spinlock_contention_pre3_4;;\n\t"
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"cmp4.ne p14, p0 = r30, r0\n\t"
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"mov b6 = r29;;\n\t"
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"mov r27=%2\n\t"
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"(p14) br.cond.spnt.many b6"
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: "=r"(ptr) : "r"(ptr), "r" (flags) : IA64_SPINLOCK_CLOBBERS);
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# else
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asm volatile ("{\n\t"
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" mov ar.ccv = r0\n\t"
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" mov r28 = ip\n\t"
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" mov r30 = 1;;\n\t"
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"}\n\t"
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"cmpxchg4.acq r30 = [%1], r30, ar.ccv;;\n\t"
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"cmp4.ne p14, p0 = r30, r0\n\t"
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"mov r27=%2\n\t"
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"(p14) brl.cond.spnt.many ia64_spinlock_contention_pre3_4;;"
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: "=r"(ptr) : "r"(ptr), "r" (flags) : IA64_SPINLOCK_CLOBBERS);
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# endif /* CONFIG_MCKINLEY */
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#else
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# ifdef CONFIG_ITANIUM
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/* don't use brl on Itanium... */
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/* mis-declare, so we get the entry-point, not it's function descriptor: */
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asm volatile ("mov r30 = 1\n\t"
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"mov r27=%2\n\t"
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"mov ar.ccv = r0;;\n\t"
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"cmpxchg4.acq r30 = [%0], r30, ar.ccv\n\t"
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"movl r29 = ia64_spinlock_contention;;\n\t"
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"cmp4.ne p14, p0 = r30, r0\n\t"
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"mov b6 = r29;;\n\t"
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"(p14) br.call.spnt.many b6 = b6"
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: "=r"(ptr) : "r"(ptr), "r" (flags) : IA64_SPINLOCK_CLOBBERS);
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# else
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asm volatile ("mov r30 = 1\n\t"
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"mov r27=%2\n\t"
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"mov ar.ccv = r0;;\n\t"
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"cmpxchg4.acq r30 = [%0], r30, ar.ccv;;\n\t"
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"cmp4.ne p14, p0 = r30, r0\n\t"
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"(p14) brl.call.spnt.many b6=ia64_spinlock_contention;;"
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: "=r"(ptr) : "r"(ptr), "r" (flags) : IA64_SPINLOCK_CLOBBERS);
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# endif /* CONFIG_MCKINLEY */
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#endif
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now_serving = *p;
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turn = ia64_fetchadd(1, p+1, acq);
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if (turn == now_serving)
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return;
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do {
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cpu_relax();
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} while (ACCESS_ONCE(*p) != turn);
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}
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#define __raw_spin_lock(lock) __raw_spin_lock_flags(lock, 0)
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static __always_inline int __ticket_spin_trylock(raw_spinlock_t *lock)
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{
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long tmp = ACCESS_ONCE(lock->lock), try;
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/* Unlock by doing an ordered store and releasing the cacheline with nta */
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static inline void __raw_spin_unlock(raw_spinlock_t *x) {
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barrier();
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asm volatile ("st4.rel.nta [%0] = r0\n\t" :: "r"(x));
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if (!(((tmp >> TICKET_SHIFT) ^ tmp) & ((1L << TICKET_SHIFT) - 1))) {
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try = tmp + (1L << TICKET_SHIFT);
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return ia64_cmpxchg(acq, &lock->lock, tmp, try, sizeof (tmp)) == tmp;
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}
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return 0;
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}
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#else /* !ASM_SUPPORTED */
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#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
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# define __raw_spin_lock(x) \
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do { \
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__u32 *ia64_spinlock_ptr = (__u32 *) (x); \
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__u64 ia64_spinlock_val; \
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ia64_spinlock_val = ia64_cmpxchg4_acq(ia64_spinlock_ptr, 1, 0); \
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if (unlikely(ia64_spinlock_val)) { \
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do { \
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while (*ia64_spinlock_ptr) \
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ia64_barrier(); \
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ia64_spinlock_val = ia64_cmpxchg4_acq(ia64_spinlock_ptr, 1, 0); \
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} while (ia64_spinlock_val); \
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} \
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} while (0)
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#define __raw_spin_unlock(x) do { barrier(); ((raw_spinlock_t *) x)->lock = 0; } while (0)
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#endif /* !ASM_SUPPORTED */
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static __always_inline void __ticket_spin_unlock(raw_spinlock_t *lock)
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{
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int *p = (int *)&lock->lock;
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#define __raw_spin_is_locked(x) ((x)->lock != 0)
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#define __raw_spin_trylock(x) (cmpxchg_acq(&(x)->lock, 0, 1) == 0)
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#define __raw_spin_unlock_wait(lock) \
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do { while (__raw_spin_is_locked(lock)) cpu_relax(); } while (0)
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(void)ia64_fetchadd(1, p, rel);
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}
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static inline int __ticket_spin_is_locked(raw_spinlock_t *lock)
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{
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long tmp = ACCESS_ONCE(lock->lock);
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return !!(((tmp >> TICKET_SHIFT) ^ tmp) & ((1L << TICKET_SHIFT) - 1));
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}
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static inline int __ticket_spin_is_contended(raw_spinlock_t *lock)
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{
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long tmp = ACCESS_ONCE(lock->lock);
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return (((tmp >> TICKET_SHIFT) - tmp) & ((1L << TICKET_SHIFT) - 1)) > 1;
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}
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static inline int __raw_spin_is_locked(raw_spinlock_t *lock)
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{
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return __ticket_spin_is_locked(lock);
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}
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static inline int __raw_spin_is_contended(raw_spinlock_t *lock)
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{
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return __ticket_spin_is_contended(lock);
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}
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#define __raw_spin_is_contended __raw_spin_is_contended
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static __always_inline void __raw_spin_lock(raw_spinlock_t *lock)
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{
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__ticket_spin_lock(lock);
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}
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static __always_inline int __raw_spin_trylock(raw_spinlock_t *lock)
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{
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return __ticket_spin_trylock(lock);
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}
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static __always_inline void __raw_spin_unlock(raw_spinlock_t *lock)
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{
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__ticket_spin_unlock(lock);
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}
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static __always_inline void __raw_spin_lock_flags(raw_spinlock_t *lock,
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unsigned long flags)
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{
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__raw_spin_lock(lock);
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}
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static inline void __raw_spin_unlock_wait(raw_spinlock_t *lock)
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{
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while (__raw_spin_is_locked(lock))
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cpu_relax();
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}
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#define __raw_read_can_lock(rw) (*(volatile int *)(rw) >= 0)
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#define __raw_write_can_lock(rw) (*(volatile int *)(rw) == 0)
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@ -6,7 +6,7 @@
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#endif
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typedef struct {
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volatile unsigned int lock;
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volatile unsigned long lock;
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} raw_spinlock_t;
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#define __RAW_SPIN_LOCK_UNLOCKED { 0 }
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@ -1130,95 +1130,6 @@ SET_REG(b5);
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#endif /* CONFIG_IA64_BRL_EMU */
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#ifdef CONFIG_SMP
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/*
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* This routine handles spinlock contention. It uses a non-standard calling
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* convention to avoid converting leaf routines into interior routines. Because
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* of this special convention, there are several restrictions:
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*
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* - do not use gp relative variables, this code is called from the kernel
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* and from modules, r1 is undefined.
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* - do not use stacked registers, the caller owns them.
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* - do not use the scratch stack space, the caller owns it.
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* - do not use any registers other than the ones listed below
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*
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* Inputs:
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* ar.pfs - saved CFM of caller
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* ar.ccv - 0 (and available for use)
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* r27 - flags from spin_lock_irqsave or 0. Must be preserved.
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* r28 - available for use.
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* r29 - available for use.
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* r30 - available for use.
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* r31 - address of lock, available for use.
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* b6 - return address
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* p14 - available for use.
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* p15 - used to track flag status.
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*
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* If you patch this code to use more registers, do not forget to update
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* the clobber lists for spin_lock() in arch/ia64/include/asm/spinlock.h.
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*/
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#if (__GNUC__ == 3 && __GNUC_MINOR__ < 3)
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GLOBAL_ENTRY(ia64_spinlock_contention_pre3_4)
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.prologue
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.save ar.pfs, r0 // this code effectively has a zero frame size
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.save rp, r28
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.body
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nop 0
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tbit.nz p15,p0=r27,IA64_PSR_I_BIT
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.restore sp // pop existing prologue after next insn
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mov b6 = r28
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.prologue
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.save ar.pfs, r0
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.altrp b6
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.body
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;;
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(p15) ssm psr.i // reenable interrupts if they were on
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// DavidM says that srlz.d is slow and is not required in this case
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.wait:
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// exponential backoff, kdb, lockmeter etc. go in here
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hint @pause
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ld4 r30=[r31] // don't use ld4.bias; if it's contended, we won't write the word
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nop 0
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;;
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cmp4.ne p14,p0=r30,r0
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(p14) br.cond.sptk.few .wait
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(p15) rsm psr.i // disable interrupts if we reenabled them
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br.cond.sptk.few b6 // lock is now free, try to acquire
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.global ia64_spinlock_contention_pre3_4_end // for kernprof
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ia64_spinlock_contention_pre3_4_end:
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END(ia64_spinlock_contention_pre3_4)
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#else
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GLOBAL_ENTRY(ia64_spinlock_contention)
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.prologue
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.altrp b6
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.body
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tbit.nz p15,p0=r27,IA64_PSR_I_BIT
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;;
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.wait:
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(p15) ssm psr.i // reenable interrupts if they were on
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// DavidM says that srlz.d is slow and is not required in this case
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.wait2:
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// exponential backoff, kdb, lockmeter etc. go in here
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hint @pause
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ld4 r30=[r31] // don't use ld4.bias; if it's contended, we won't write the word
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;;
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cmp4.ne p14,p0=r30,r0
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mov r30 = 1
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(p14) br.cond.sptk.few .wait2
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(p15) rsm psr.i // disable interrupts if we reenabled them
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;;
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cmpxchg4.acq r30=[r31], r30, ar.ccv
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;;
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cmp4.ne p14,p0=r0,r30
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(p14) br.cond.sptk.few .wait
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br.ret.sptk.many b6 // lock is now taken
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END(ia64_spinlock_contention)
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#endif
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#ifdef CONFIG_HOTPLUG_CPU
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GLOBAL_ENTRY(ia64_jump_to_sal)
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@ -84,26 +84,6 @@ EXPORT_SYMBOL(ia64_save_scratch_fpregs);
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#include <asm/unwind.h>
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EXPORT_SYMBOL(unw_init_running);
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#ifdef ASM_SUPPORTED
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# ifdef CONFIG_SMP
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# if (__GNUC__ == 3 && __GNUC_MINOR__ < 3)
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/*
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* This is not a normal routine and we don't want a function descriptor for it, so we use
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* a fake declaration here.
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*/
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extern char ia64_spinlock_contention_pre3_4;
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EXPORT_SYMBOL(ia64_spinlock_contention_pre3_4);
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# else
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/*
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* This is not a normal routine and we don't want a function descriptor for it, so we use
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* a fake declaration here.
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*/
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extern char ia64_spinlock_contention;
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EXPORT_SYMBOL(ia64_spinlock_contention);
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# endif
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# endif
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#endif
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#if defined(CONFIG_IA64_ESI) || defined(CONFIG_IA64_ESI_MODULE)
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extern void esi_call_phys (void);
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EXPORT_SYMBOL_GPL(esi_call_phys);
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@ -32,24 +32,6 @@ typedef struct
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u64 *prev_pfs_loc; /* state for WAR for old spinlock ool code */
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} ia64_backtrace_t;
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#if (__GNUC__ == 3 && __GNUC_MINOR__ < 3)
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/*
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* Returns non-zero if the PC is in the spinlock contention out-of-line code
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* with non-standard calling sequence (on older compilers).
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*/
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static __inline__ int in_old_ool_spinlock_code(unsigned long pc)
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{
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extern const char ia64_spinlock_contention_pre3_4[] __attribute__ ((weak));
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extern const char ia64_spinlock_contention_pre3_4_end[] __attribute__ ((weak));
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unsigned long sc_start = (unsigned long)ia64_spinlock_contention_pre3_4;
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unsigned long sc_end = (unsigned long)ia64_spinlock_contention_pre3_4_end;
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return (sc_start && sc_end && pc >= sc_start && pc < sc_end);
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}
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#else
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/* Newer spinlock code does a proper br.call and works fine with the unwinder */
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#define in_old_ool_spinlock_code(pc) 0
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#endif
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/* Returns non-zero if the PC is in the Interrupt Vector Table */
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static __inline__ int in_ivt_code(unsigned long pc)
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{
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@ -80,7 +62,7 @@ static __inline__ int next_frame(ia64_backtrace_t *bt)
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*/
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if (bt->prev_pfs_loc && bt->regs && bt->frame.pfs_loc == bt->prev_pfs_loc)
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bt->frame.pfs_loc = &bt->regs->ar_pfs;
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bt->prev_pfs_loc = (in_old_ool_spinlock_code(bt->frame.ip) ? bt->frame.pfs_loc : NULL);
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bt->prev_pfs_loc = NULL;
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return unw_unwind(&bt->frame) == 0;
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}
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