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perf/x86/intel: Expose LBR callstack to user space tooling
With LBR call stack feature enable, there are three callchain options. Enable the 3rd callchain option (LBR callstack) to user space tooling. Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Arnaldo Carvalho de Melo <acme@kernel.org> Cc: Andy Lutomirski <luto@amacapital.net> Cc: Kan Liang <kan.liang@intel.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Paul Mackerras <paulus@samba.org> Cc: Vince Weaver <vincent.weaver@maine.edu> Cc: linux-api@vger.kernel.org Link: http://lkml.kernel.org/r/20141105093759.GQ10501@worktop.programming.kicks-ass.net Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@ -523,14 +523,6 @@ struct x86_perf_task_context {
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int lbr_stack_state;
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};
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enum {
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PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = PERF_SAMPLE_BRANCH_MAX_SHIFT,
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PERF_SAMPLE_BRANCH_SELECT_MAP_SIZE,
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PERF_SAMPLE_BRANCH_CALL_STACK =
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1U << PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT,
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};
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#define x86_add_quirk(func_) \
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do { \
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static struct x86_pmu_quirk __quirk __initdata = { \
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@ -537,7 +537,7 @@ static int intel_pmu_setup_hw_lbr_filter(struct perf_event *event)
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u64 mask = 0, v;
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int i;
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for (i = 0; i < PERF_SAMPLE_BRANCH_SELECT_MAP_SIZE; i++) {
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for (i = 0; i < PERF_SAMPLE_BRANCH_MAX_SHIFT; i++) {
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if (!(br_type & (1ULL << i)))
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continue;
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@ -821,7 +821,7 @@ intel_pmu_lbr_filter(struct cpu_hw_events *cpuc)
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/*
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* Map interface branch filters onto LBR filters
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*/
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static const int nhm_lbr_sel_map[PERF_SAMPLE_BRANCH_SELECT_MAP_SIZE] = {
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static const int nhm_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX_SHIFT] = {
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[PERF_SAMPLE_BRANCH_ANY_SHIFT] = LBR_ANY,
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[PERF_SAMPLE_BRANCH_USER_SHIFT] = LBR_USER,
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[PERF_SAMPLE_BRANCH_KERNEL_SHIFT] = LBR_KERNEL,
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@ -840,7 +840,7 @@ static const int nhm_lbr_sel_map[PERF_SAMPLE_BRANCH_SELECT_MAP_SIZE] = {
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[PERF_SAMPLE_BRANCH_COND_SHIFT] = LBR_JCC,
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};
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static const int snb_lbr_sel_map[PERF_SAMPLE_BRANCH_SELECT_MAP_SIZE] = {
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static const int snb_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX_SHIFT] = {
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[PERF_SAMPLE_BRANCH_ANY_SHIFT] = LBR_ANY,
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[PERF_SAMPLE_BRANCH_USER_SHIFT] = LBR_USER,
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[PERF_SAMPLE_BRANCH_KERNEL_SHIFT] = LBR_KERNEL,
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@ -852,7 +852,7 @@ static const int snb_lbr_sel_map[PERF_SAMPLE_BRANCH_SELECT_MAP_SIZE] = {
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[PERF_SAMPLE_BRANCH_COND_SHIFT] = LBR_JCC,
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};
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static const int hsw_lbr_sel_map[PERF_SAMPLE_BRANCH_SELECT_MAP_SIZE] = {
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static const int hsw_lbr_sel_map[PERF_SAMPLE_BRANCH_MAX_SHIFT] = {
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[PERF_SAMPLE_BRANCH_ANY_SHIFT] = LBR_ANY,
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[PERF_SAMPLE_BRANCH_USER_SHIFT] = LBR_USER,
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[PERF_SAMPLE_BRANCH_KERNEL_SHIFT] = LBR_KERNEL,
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@ -166,6 +166,8 @@ enum perf_branch_sample_type_shift {
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PERF_SAMPLE_BRANCH_NO_TX_SHIFT = 9, /* not in transaction */
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PERF_SAMPLE_BRANCH_COND_SHIFT = 10, /* conditional branches */
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PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT = 11, /* call/ret stack */
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PERF_SAMPLE_BRANCH_MAX_SHIFT /* non-ABI */
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};
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@ -175,18 +177,16 @@ enum perf_branch_sample_type {
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PERF_SAMPLE_BRANCH_HV = 1U << PERF_SAMPLE_BRANCH_HV_SHIFT,
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PERF_SAMPLE_BRANCH_ANY = 1U << PERF_SAMPLE_BRANCH_ANY_SHIFT,
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PERF_SAMPLE_BRANCH_ANY_CALL =
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1U << PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT,
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PERF_SAMPLE_BRANCH_ANY_RETURN =
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1U << PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT,
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PERF_SAMPLE_BRANCH_IND_CALL =
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1U << PERF_SAMPLE_BRANCH_IND_CALL_SHIFT,
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PERF_SAMPLE_BRANCH_ABORT_TX =
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1U << PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT,
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PERF_SAMPLE_BRANCH_ANY_CALL = 1U << PERF_SAMPLE_BRANCH_ANY_CALL_SHIFT,
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PERF_SAMPLE_BRANCH_ANY_RETURN = 1U << PERF_SAMPLE_BRANCH_ANY_RETURN_SHIFT,
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PERF_SAMPLE_BRANCH_IND_CALL = 1U << PERF_SAMPLE_BRANCH_IND_CALL_SHIFT,
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PERF_SAMPLE_BRANCH_ABORT_TX = 1U << PERF_SAMPLE_BRANCH_ABORT_TX_SHIFT,
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PERF_SAMPLE_BRANCH_IN_TX = 1U << PERF_SAMPLE_BRANCH_IN_TX_SHIFT,
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PERF_SAMPLE_BRANCH_NO_TX = 1U << PERF_SAMPLE_BRANCH_NO_TX_SHIFT,
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PERF_SAMPLE_BRANCH_COND = 1U << PERF_SAMPLE_BRANCH_COND_SHIFT,
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PERF_SAMPLE_BRANCH_CALL_STACK = 1U << PERF_SAMPLE_BRANCH_CALL_STACK_SHIFT,
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PERF_SAMPLE_BRANCH_MAX = 1U << PERF_SAMPLE_BRANCH_MAX_SHIFT,
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};
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