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ARM: 9297/1: vfp: avoid unbalanced stack on 'success' return path
Commitc76c6c4ecb
("ARM: 9294/2: vfp: Fix broken softirq handling with instrumentation enabled") updated the VFP exception entry logic to go via a C function, so that we get the compiler's version of local_bh_disable(), which may be instrumented, and isn't generally callable from assembler. However, this assumes that passing an alternative 'success' return address works in C as it does in asm, and this is only the case if the C calls in question are tail calls, as otherwise, the stack will need some unwinding as well. I have already sent patches to the list that replace most of the asm logic with C code, and so it is preferable to have a minimal fix that addresses the issue and can be backported along with the commit that it fixes to v6.3 from v6.4. Hopefully, we can land the C conversion for v6.5. So instead of passing the 'success' return address as a function argument, pass the stack address from where to pop it so that both LR and SP have the expected value. Fixes:c76c6c4ecb
("ARM: 9294/2: vfp: Fix broken softirq handling with ...") Reported-by: syzbot+d4b00edc2d0c910d4bf4@syzkaller.appspotmail.com Tested-by: syzbot+d4b00edc2d0c910d4bf4@syzkaller.appspotmail.com Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Tested-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Ard Biesheuvel <ardb@kernel.org> Tested-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Russell King (Oracle) <rmk+kernel@armlinux.org.uk>
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@ -23,6 +23,9 @@
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@
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ENTRY(do_vfp)
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mov r1, r10
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mov r3, r9
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b vfp_entry
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str lr, [sp, #-8]!
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add r3, sp, #4
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str r9, [r3]
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bl vfp_entry
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ldr pc, [sp], #8
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ENDPROC(do_vfp)
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@ -172,13 +172,14 @@ vfp_hw_state_valid:
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@ out before setting an FPEXC that
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@ stops us reading stuff
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VFPFMXR FPEXC, r1 @ Restore FPEXC last
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mov sp, r3 @ we think we have handled things
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pop {lr}
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sub r2, r2, #4 @ Retry current instruction - if Thumb
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str r2, [sp, #S_PC] @ mode it's two 16-bit instructions,
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@ else it's one 32-bit instruction, so
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@ always subtract 4 from the following
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@ instruction address.
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mov lr, r3 @ we think we have handled things
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local_bh_enable_and_ret:
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adr r0, .
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mov r1, #SOFTIRQ_DISABLE_OFFSET
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@ -209,8 +210,9 @@ skip:
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process_exception:
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DBGSTR "bounce"
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mov sp, r3 @ setup for a return to the user code.
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pop {lr}
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mov r2, sp @ nothing stacked - regdump is at TOS
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mov lr, r3 @ setup for a return to the user code.
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@ Now call the C code to package up the bounce to the support code
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@ r0 holds the trigger instruction
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