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clk: imx: clk-composite-93: check white_list

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The CCM ROOT AUTHEN register WHITE_LIST indicate:
Each bit in this field represent for one domain. Bit16~Bit31 represent
for DOMAIN0~DOMAIN15 respectively. Only corresponding bit of the domains
is set to 1 can change the registers of this Clock Root.

i.MX93 DID is 3, so if BIT(3 + WHITE_LIST_SHIFT) is 0, the clk should be
set to read only. To make the imx93_clk_composite_flags be reusable,
add a new parameter named did(domain id);

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20220830033137.4149542-5-peng.fan@oss.nxp.com
This commit is contained in:
Peng Fan 2022-08-30 11:31:33 +08:00 committed by Abel Vesa
parent 4a3de5aa77
commit 2b66f02e2d
3 changed files with 10 additions and 5 deletions
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8
drivers/clk/imx/clk-composite-93.c
View File

@ -28,6 +28,8 @@
#define TZ_NS_SHIFT 9
#define TZ_NS_MASK BIT(9)
#define WHITE_LIST_SHIFT 16
static int imx93_clk_composite_wait_ready(struct clk_hw *hw, void __iomem *reg)
{
int ret;
@ -180,7 +182,7 @@ static const struct clk_ops imx93_clk_composite_mux_ops = {
};
struct clk_hw *imx93_clk_composite_flags(const char *name, const char * const *parent_names,
int num_parents, void __iomem *reg,
int num_parents, void __iomem *reg, u32 domain_id,
unsigned long flags)
{
struct clk_hw *hw = ERR_PTR(-ENOMEM), *mux_hw;
@ -189,6 +191,7 @@ struct clk_hw *imx93_clk_composite_flags(const char *name, const char * const *p
struct clk_gate *gate = NULL;
struct clk_mux *mux = NULL;
bool clk_ro = false;
u32 authen;
mux = kzalloc(sizeof(*mux), GFP_KERNEL);
if (!mux)
@ -211,7 +214,8 @@ struct clk_hw *imx93_clk_composite_flags(const char *name, const char * const *p
div->lock = &imx_ccm_lock;
div->flags = CLK_DIVIDER_ROUND_CLOSEST;
if (!(readl(reg + AUTHEN_OFFSET) & TZ_NS_MASK))
authen = readl(reg + AUTHEN_OFFSET);
if (!(authen & TZ_NS_MASK) || !(authen & BIT(WHITE_LIST_SHIFT + domain_id)))
clk_ro = true;
if (clk_ro) {

2
drivers/clk/imx/clk-imx93.c
View File

@ -293,7 +293,7 @@ static int imx93_clocks_probe(struct platform_device *pdev)
root = &root_array[i];
clks[root->clk] = imx93_clk_composite_flags(root->name,
parent_names[root->sel],
4, base + root->off,
4, base + root->off, 3,
root->flags);
}

5
drivers/clk/imx/clk.h
View File

@ -445,9 +445,10 @@ struct clk_hw *imx93_clk_composite_flags(const char *name,
const char * const *parent_names,
int num_parents,
void __iomem *reg,
u32 domain_id,
unsigned long flags);
#define imx93_clk_composite(name, parent_names, num_parents, reg) \
imx93_clk_composite_flags(name, parent_names, num_parents, reg, \
#define imx93_clk_composite(name, parent_names, num_parents, reg, domain_id) \
imx93_clk_composite_flags(name, parent_names, num_parents, reg, domain_id \
CLK_SET_RATE_NO_REPARENT | CLK_OPS_PARENT_ENABLE)
struct clk_hw *imx_clk_hw_divider_gate(const char *name, const char *parent_name,