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mtd: m25p80: Fix 4 byte addressing mode for Micron devices.
According to the datasheet for Micron n25q256a (N25Q256A13ESF40F) 4-byte addressing mode should be entered as follows: <quote> To enter or exit the 4-byte address mode, the WRITE ENABLE command must be executed to set the write enable latch bit to 1. (Note: The WRITE ENABLE command must NOT be executed on the N25Q256A83ESF40x and N25Q256A83E1240x devices.) S# must be driven LOW. The effect of the command is immediate; after the command has been executed, the write enable latch bit is cleared to 0. </quote> Micron's portable way to perform this for all types of Micron flash is to first issue a write enable, then switch the addressing mode followed by a write disable to avoid leaving the flash in a write- able state. Signed-off-by: Elie De Brauwer <eliedebrauwer@email.com> [Brian: reworked a bit] Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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@ -168,12 +168,25 @@ static inline int write_disable(struct m25p *flash)
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*/
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static inline int set_4byte(struct m25p *flash, u32 jedec_id, int enable)
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{
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int status;
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bool need_wren = false;
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switch (JEDEC_MFR(jedec_id)) {
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case CFI_MFR_MACRONIX:
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case CFI_MFR_ST: /* Micron, actually */
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/* Some Micron need WREN command; all will accept it */
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need_wren = true;
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case CFI_MFR_MACRONIX:
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case 0xEF /* winbond */:
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if (need_wren)
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write_enable(flash);
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flash->command[0] = enable ? OPCODE_EN4B : OPCODE_EX4B;
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return spi_write(flash->spi, flash->command, 1);
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status = spi_write(flash->spi, flash->command, 1);
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if (need_wren)
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write_disable(flash);
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return status;
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default:
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/* Spansion style */
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flash->command[0] = OPCODE_BRWR;
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