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RDMA/erdma: Add cmdq implementation
Cmdq is the main control plane channel between erdma driver and hardware. After erdma device is initialized, the cmdq channel will be active in the whole lifecycle of this driver. This commit also includes two modifications from Christophe, one is using the bitmap API to allocate bitmaps instead of hand-writing, and another is using the non-atomic bitmap API when applicable. Link: https://lore.kernel.org/r/20220727014927.76564-5-chengyou@linux.alibaba.com Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Signed-off-by: Cheng Xu <chengyou@linux.alibaba.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
This commit is contained in:
Cheng Xu
Jason Gunthorpe
parent
bee85e0e31
commit
2af541bf8e
493
drivers/infiniband/hw/erdma/erdma_cmdq.c
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493
drivers/infiniband/hw/erdma/erdma_cmdq.c
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@ -0,0 +1,493 @@
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// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
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/* Authors: Cheng Xu <chengyou@linux.alibaba.com> */
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/* Kai Shen <kaishen@linux.alibaba.com> */
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/* Copyright (c) 2020-2022, Alibaba Group. */
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#include <linux/kernel.h>
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#include <linux/pci.h>
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#include <linux/types.h>
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#include "erdma.h"
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#include "erdma_hw.h"
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#include "erdma_verbs.h"
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static void arm_cmdq_cq(struct erdma_cmdq *cmdq)
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{
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struct erdma_dev *dev = container_of(cmdq, struct erdma_dev, cmdq);
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u64 db_data = FIELD_PREP(ERDMA_CQDB_CI_MASK, cmdq->cq.ci) |
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FIELD_PREP(ERDMA_CQDB_ARM_MASK, 1) |
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FIELD_PREP(ERDMA_CQDB_CMDSN_MASK, cmdq->cq.cmdsn) |
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FIELD_PREP(ERDMA_CQDB_IDX_MASK, cmdq->cq.cmdsn);
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*cmdq->cq.db_record = db_data;
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writeq(db_data, dev->func_bar + ERDMA_CMDQ_CQDB_REG);
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atomic64_inc(&cmdq->cq.armed_num);
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}
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static void kick_cmdq_db(struct erdma_cmdq *cmdq)
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{
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struct erdma_dev *dev = container_of(cmdq, struct erdma_dev, cmdq);
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u64 db_data = FIELD_PREP(ERDMA_CMD_HDR_WQEBB_INDEX_MASK, cmdq->sq.pi);
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*cmdq->sq.db_record = db_data;
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writeq(db_data, dev->func_bar + ERDMA_CMDQ_SQDB_REG);
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}
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static struct erdma_comp_wait *get_comp_wait(struct erdma_cmdq *cmdq)
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{
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int comp_idx;
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spin_lock(&cmdq->lock);
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comp_idx = find_first_zero_bit(cmdq->comp_wait_bitmap,
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cmdq->max_outstandings);
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if (comp_idx == cmdq->max_outstandings) {
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spin_unlock(&cmdq->lock);
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return ERR_PTR(-ENOMEM);
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}
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__set_bit(comp_idx, cmdq->comp_wait_bitmap);
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spin_unlock(&cmdq->lock);
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return &cmdq->wait_pool[comp_idx];
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}
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static void put_comp_wait(struct erdma_cmdq *cmdq,
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struct erdma_comp_wait *comp_wait)
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{
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int used;
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cmdq->wait_pool[comp_wait->ctx_id].cmd_status = ERDMA_CMD_STATUS_INIT;
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spin_lock(&cmdq->lock);
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used = __test_and_clear_bit(comp_wait->ctx_id, cmdq->comp_wait_bitmap);
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spin_unlock(&cmdq->lock);
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WARN_ON(!used);
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}
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static int erdma_cmdq_wait_res_init(struct erdma_dev *dev,
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struct erdma_cmdq *cmdq)
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{
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int i;
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cmdq->wait_pool =
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devm_kcalloc(&dev->pdev->dev, cmdq->max_outstandings,
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sizeof(struct erdma_comp_wait), GFP_KERNEL);
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if (!cmdq->wait_pool)
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return -ENOMEM;
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spin_lock_init(&cmdq->lock);
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cmdq->comp_wait_bitmap = devm_bitmap_zalloc(
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&dev->pdev->dev, cmdq->max_outstandings, GFP_KERNEL);
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if (!cmdq->comp_wait_bitmap)
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return -ENOMEM;
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for (i = 0; i < cmdq->max_outstandings; i++) {
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init_completion(&cmdq->wait_pool[i].wait_event);
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cmdq->wait_pool[i].ctx_id = i;
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}
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return 0;
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}
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static int erdma_cmdq_sq_init(struct erdma_dev *dev)
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{
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struct erdma_cmdq *cmdq = &dev->cmdq;
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struct erdma_cmdq_sq *sq = &cmdq->sq;
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u32 buf_size;
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sq->wqebb_cnt = SQEBB_COUNT(ERDMA_CMDQ_SQE_SIZE);
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sq->depth = cmdq->max_outstandings * sq->wqebb_cnt;
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buf_size = sq->depth << SQEBB_SHIFT;
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sq->qbuf =
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dma_alloc_coherent(&dev->pdev->dev, WARPPED_BUFSIZE(buf_size),
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&sq->qbuf_dma_addr, GFP_KERNEL);
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if (!sq->qbuf)
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return -ENOMEM;
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sq->db_record = (u64 *)(sq->qbuf + buf_size);
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spin_lock_init(&sq->lock);
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erdma_reg_write32(dev, ERDMA_REGS_CMDQ_SQ_ADDR_H_REG,
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upper_32_bits(sq->qbuf_dma_addr));
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erdma_reg_write32(dev, ERDMA_REGS_CMDQ_SQ_ADDR_L_REG,
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lower_32_bits(sq->qbuf_dma_addr));
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erdma_reg_write32(dev, ERDMA_REGS_CMDQ_DEPTH_REG, sq->depth);
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erdma_reg_write64(dev, ERDMA_CMDQ_SQ_DB_HOST_ADDR_REG,
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sq->qbuf_dma_addr + buf_size);
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return 0;
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}
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static int erdma_cmdq_cq_init(struct erdma_dev *dev)
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{
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struct erdma_cmdq *cmdq = &dev->cmdq;
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struct erdma_cmdq_cq *cq = &cmdq->cq;
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u32 buf_size;
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cq->depth = cmdq->sq.depth;
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buf_size = cq->depth << CQE_SHIFT;
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cq->qbuf =
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dma_alloc_coherent(&dev->pdev->dev, WARPPED_BUFSIZE(buf_size),
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&cq->qbuf_dma_addr, GFP_KERNEL | __GFP_ZERO);
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if (!cq->qbuf)
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return -ENOMEM;
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spin_lock_init(&cq->lock);
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cq->db_record = (u64 *)(cq->qbuf + buf_size);
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atomic64_set(&cq->armed_num, 0);
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erdma_reg_write32(dev, ERDMA_REGS_CMDQ_CQ_ADDR_H_REG,
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upper_32_bits(cq->qbuf_dma_addr));
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erdma_reg_write32(dev, ERDMA_REGS_CMDQ_CQ_ADDR_L_REG,
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lower_32_bits(cq->qbuf_dma_addr));
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erdma_reg_write64(dev, ERDMA_CMDQ_CQ_DB_HOST_ADDR_REG,
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cq->qbuf_dma_addr + buf_size);
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return 0;
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}
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static int erdma_cmdq_eq_init(struct erdma_dev *dev)
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{
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struct erdma_cmdq *cmdq = &dev->cmdq;
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struct erdma_eq *eq = &cmdq->eq;
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u32 buf_size;
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eq->depth = cmdq->max_outstandings;
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buf_size = eq->depth << EQE_SHIFT;
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eq->qbuf =
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dma_alloc_coherent(&dev->pdev->dev, WARPPED_BUFSIZE(buf_size),
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&eq->qbuf_dma_addr, GFP_KERNEL | __GFP_ZERO);
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if (!eq->qbuf)
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return -ENOMEM;
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spin_lock_init(&eq->lock);
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atomic64_set(&eq->event_num, 0);
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eq->db_addr =
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(u64 __iomem *)(dev->func_bar + ERDMA_REGS_CEQ_DB_BASE_REG);
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eq->db_record = (u64 *)(eq->qbuf + buf_size);
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erdma_reg_write32(dev, ERDMA_REGS_CMDQ_EQ_ADDR_H_REG,
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upper_32_bits(eq->qbuf_dma_addr));
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erdma_reg_write32(dev, ERDMA_REGS_CMDQ_EQ_ADDR_L_REG,
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lower_32_bits(eq->qbuf_dma_addr));
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erdma_reg_write32(dev, ERDMA_REGS_CMDQ_EQ_DEPTH_REG, eq->depth);
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erdma_reg_write64(dev, ERDMA_CMDQ_EQ_DB_HOST_ADDR_REG,
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eq->qbuf_dma_addr + buf_size);
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return 0;
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}
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int erdma_cmdq_init(struct erdma_dev *dev)
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{
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int err, i;
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struct erdma_cmdq *cmdq = &dev->cmdq;
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u32 sts, ctrl;
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cmdq->max_outstandings = ERDMA_CMDQ_MAX_OUTSTANDING;
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cmdq->use_event = false;
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sema_init(&cmdq->credits, cmdq->max_outstandings);
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err = erdma_cmdq_wait_res_init(dev, cmdq);
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if (err)
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return err;
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err = erdma_cmdq_sq_init(dev);
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if (err)
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return err;
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err = erdma_cmdq_cq_init(dev);
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if (err)
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goto err_destroy_sq;
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err = erdma_cmdq_eq_init(dev);
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if (err)
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goto err_destroy_cq;
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ctrl = FIELD_PREP(ERDMA_REG_DEV_CTRL_INIT_MASK, 1);
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erdma_reg_write32(dev, ERDMA_REGS_DEV_CTRL_REG, ctrl);
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for (i = 0; i < ERDMA_WAIT_DEV_DONE_CNT; i++) {
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sts = erdma_reg_read32_filed(dev, ERDMA_REGS_DEV_ST_REG,
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ERDMA_REG_DEV_ST_INIT_DONE_MASK);
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if (sts)
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break;
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msleep(ERDMA_REG_ACCESS_WAIT_MS);
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}
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if (i == ERDMA_WAIT_DEV_DONE_CNT) {
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dev_err(&dev->pdev->dev, "wait init done failed.\n");
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err = -ETIMEDOUT;
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goto err_destroy_eq;
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}
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set_bit(ERDMA_CMDQ_STATE_OK_BIT, &cmdq->state);
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return 0;
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err_destroy_eq:
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dma_free_coherent(&dev->pdev->dev,
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(cmdq->eq.depth << EQE_SHIFT) +
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ERDMA_EXTRA_BUFFER_SIZE,
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cmdq->eq.qbuf, cmdq->eq.qbuf_dma_addr);
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err_destroy_cq:
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dma_free_coherent(&dev->pdev->dev,
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(cmdq->cq.depth << CQE_SHIFT) +
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ERDMA_EXTRA_BUFFER_SIZE,
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cmdq->cq.qbuf, cmdq->cq.qbuf_dma_addr);
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err_destroy_sq:
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dma_free_coherent(&dev->pdev->dev,
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(cmdq->sq.depth << SQEBB_SHIFT) +
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ERDMA_EXTRA_BUFFER_SIZE,
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cmdq->sq.qbuf, cmdq->sq.qbuf_dma_addr);
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return err;
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}
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void erdma_finish_cmdq_init(struct erdma_dev *dev)
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{
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/* after device init successfully, change cmdq to event mode. */
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dev->cmdq.use_event = true;
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arm_cmdq_cq(&dev->cmdq);
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}
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void erdma_cmdq_destroy(struct erdma_dev *dev)
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{
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struct erdma_cmdq *cmdq = &dev->cmdq;
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clear_bit(ERDMA_CMDQ_STATE_OK_BIT, &cmdq->state);
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dma_free_coherent(&dev->pdev->dev,
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(cmdq->eq.depth << EQE_SHIFT) +
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ERDMA_EXTRA_BUFFER_SIZE,
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cmdq->eq.qbuf, cmdq->eq.qbuf_dma_addr);
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dma_free_coherent(&dev->pdev->dev,
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(cmdq->sq.depth << SQEBB_SHIFT) +
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ERDMA_EXTRA_BUFFER_SIZE,
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cmdq->sq.qbuf, cmdq->sq.qbuf_dma_addr);
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dma_free_coherent(&dev->pdev->dev,
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(cmdq->cq.depth << CQE_SHIFT) +
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ERDMA_EXTRA_BUFFER_SIZE,
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cmdq->cq.qbuf, cmdq->cq.qbuf_dma_addr);
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}
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static void *get_next_valid_cmdq_cqe(struct erdma_cmdq *cmdq)
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{
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__be32 *cqe = get_queue_entry(cmdq->cq.qbuf, cmdq->cq.ci,
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cmdq->cq.depth, CQE_SHIFT);
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u32 owner = FIELD_GET(ERDMA_CQE_HDR_OWNER_MASK,
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__be32_to_cpu(READ_ONCE(*cqe)));
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return owner ^ !!(cmdq->cq.ci & cmdq->cq.depth) ? cqe : NULL;
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}
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static void push_cmdq_sqe(struct erdma_cmdq *cmdq, u64 *req, size_t req_len,
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struct erdma_comp_wait *comp_wait)
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{
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__le64 *wqe;
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u64 hdr = *req;
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comp_wait->cmd_status = ERDMA_CMD_STATUS_ISSUED;
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reinit_completion(&comp_wait->wait_event);
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comp_wait->sq_pi = cmdq->sq.pi;
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wqe = get_queue_entry(cmdq->sq.qbuf, cmdq->sq.pi, cmdq->sq.depth,
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SQEBB_SHIFT);
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memcpy(wqe, req, req_len);
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cmdq->sq.pi += cmdq->sq.wqebb_cnt;
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hdr |= FIELD_PREP(ERDMA_CMD_HDR_WQEBB_INDEX_MASK, cmdq->sq.pi) |
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FIELD_PREP(ERDMA_CMD_HDR_CONTEXT_COOKIE_MASK,
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comp_wait->ctx_id) |
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FIELD_PREP(ERDMA_CMD_HDR_WQEBB_CNT_MASK, cmdq->sq.wqebb_cnt - 1);
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*wqe = cpu_to_le64(hdr);
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kick_cmdq_db(cmdq);
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}
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static int erdma_poll_single_cmd_completion(struct erdma_cmdq *cmdq)
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{
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struct erdma_comp_wait *comp_wait;
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u32 hdr0, sqe_idx;
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__be32 *cqe;
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u16 ctx_id;
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u64 *sqe;
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int i;
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cqe = get_next_valid_cmdq_cqe(cmdq);
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if (!cqe)
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return -EAGAIN;
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cmdq->cq.ci++;
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dma_rmb();
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hdr0 = __be32_to_cpu(*cqe);
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sqe_idx = __be32_to_cpu(*(cqe + 1));
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sqe = get_queue_entry(cmdq->sq.qbuf, sqe_idx, cmdq->sq.depth,
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SQEBB_SHIFT);
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ctx_id = FIELD_GET(ERDMA_CMD_HDR_CONTEXT_COOKIE_MASK, *sqe);
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comp_wait = &cmdq->wait_pool[ctx_id];
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if (comp_wait->cmd_status != ERDMA_CMD_STATUS_ISSUED)
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return -EIO;
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comp_wait->cmd_status = ERDMA_CMD_STATUS_FINISHED;
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comp_wait->comp_status = FIELD_GET(ERDMA_CQE_HDR_SYNDROME_MASK, hdr0);
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cmdq->sq.ci += cmdq->sq.wqebb_cnt;
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for (i = 0; i < 4; i++)
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comp_wait->comp_data[i] = __be32_to_cpu(*(cqe + 2 + i));
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if (cmdq->use_event)
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complete(&comp_wait->wait_event);
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return 0;
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}
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static void erdma_polling_cmd_completions(struct erdma_cmdq *cmdq)
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{
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unsigned long flags;
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u16 comp_num;
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spin_lock_irqsave(&cmdq->cq.lock, flags);
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/* We must have less than # of max_outstandings
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* completions at one time.
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*/
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for (comp_num = 0; comp_num < cmdq->max_outstandings; comp_num++)
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if (erdma_poll_single_cmd_completion(cmdq))
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break;
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if (comp_num && cmdq->use_event)
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arm_cmdq_cq(cmdq);
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spin_unlock_irqrestore(&cmdq->cq.lock, flags);
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}
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void erdma_cmdq_completion_handler(struct erdma_cmdq *cmdq)
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{
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int got_event = 0;
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if (!test_bit(ERDMA_CMDQ_STATE_OK_BIT, &cmdq->state) ||
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!cmdq->use_event)
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return;
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while (get_next_valid_eqe(&cmdq->eq)) {
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cmdq->eq.ci++;
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got_event++;
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}
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if (got_event) {
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cmdq->cq.cmdsn++;
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erdma_polling_cmd_completions(cmdq);
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}
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notify_eq(&cmdq->eq);
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}
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static int erdma_poll_cmd_completion(struct erdma_comp_wait *comp_ctx,
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struct erdma_cmdq *cmdq, u32 timeout)
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{
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unsigned long comp_timeout = jiffies + msecs_to_jiffies(timeout);
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while (1) {
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erdma_polling_cmd_completions(cmdq);
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if (comp_ctx->cmd_status != ERDMA_CMD_STATUS_ISSUED)
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break;
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if (time_is_before_jiffies(comp_timeout))
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return -ETIME;
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msleep(20);
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}
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return 0;
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}
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static int erdma_wait_cmd_completion(struct erdma_comp_wait *comp_ctx,
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struct erdma_cmdq *cmdq, u32 timeout)
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{
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unsigned long flags = 0;
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|
||||
wait_for_completion_timeout(&comp_ctx->wait_event,
|
||||
msecs_to_jiffies(timeout));
|
||||
|
||||
if (unlikely(comp_ctx->cmd_status != ERDMA_CMD_STATUS_FINISHED)) {
|
||||
spin_lock_irqsave(&cmdq->cq.lock, flags);
|
||||
comp_ctx->cmd_status = ERDMA_CMD_STATUS_TIMEOUT;
|
||||
spin_unlock_irqrestore(&cmdq->cq.lock, flags);
|
||||
return -ETIME;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
void erdma_cmdq_build_reqhdr(u64 *hdr, u32 mod, u32 op)
|
||||
{
|
||||
*hdr = FIELD_PREP(ERDMA_CMD_HDR_SUB_MOD_MASK, mod) |
|
||||
FIELD_PREP(ERDMA_CMD_HDR_OPCODE_MASK, op);
|
||||
}
|
||||
|
||||
int erdma_post_cmd_wait(struct erdma_cmdq *cmdq, u64 *req, u32 req_size,
|
||||
u64 *resp0, u64 *resp1)
|
||||
{
|
||||
struct erdma_comp_wait *comp_wait;
|
||||
int ret;
|
||||
|
||||
if (!test_bit(ERDMA_CMDQ_STATE_OK_BIT, &cmdq->state))
|
||||
return -ENODEV;
|
||||
|
||||
down(&cmdq->credits);
|
||||
|
||||
comp_wait = get_comp_wait(cmdq);
|
||||
if (IS_ERR(comp_wait)) {
|
||||
clear_bit(ERDMA_CMDQ_STATE_OK_BIT, &cmdq->state);
|
||||
set_bit(ERDMA_CMDQ_STATE_CTX_ERR_BIT, &cmdq->state);
|
||||
up(&cmdq->credits);
|
||||
return PTR_ERR(comp_wait);
|
||||
}
|
||||
|
||||
spin_lock(&cmdq->sq.lock);
|
||||
push_cmdq_sqe(cmdq, req, req_size, comp_wait);
|
||||
spin_unlock(&cmdq->sq.lock);
|
||||
|
||||
if (cmdq->use_event)
|
||||
ret = erdma_wait_cmd_completion(comp_wait, cmdq,
|
||||
ERDMA_CMDQ_TIMEOUT_MS);
|
||||
else
|
||||
ret = erdma_poll_cmd_completion(comp_wait, cmdq,
|
||||
ERDMA_CMDQ_TIMEOUT_MS);
|
||||
|
||||
if (ret) {
|
||||
set_bit(ERDMA_CMDQ_STATE_TIMEOUT_BIT, &cmdq->state);
|
||||
clear_bit(ERDMA_CMDQ_STATE_OK_BIT, &cmdq->state);
|
||||
goto out;
|
||||
}
|
||||
|
||||
if (comp_wait->comp_status)
|
||||
ret = -EIO;
|
||||
|
||||
if (resp0 && resp1) {
|
||||
*resp0 = *((u64 *)&comp_wait->comp_data[0]);
|
||||
*resp1 = *((u64 *)&comp_wait->comp_data[2]);
|
||||
}
|
||||
put_comp_wait(cmdq, comp_wait);
|
||||
|
||||
out:
|
||||
up(&cmdq->credits);
|
||||
|
||||
return ret;
|
||||
}
|
||||
Loading…
Reference in New Issue
Block a user