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arm64: dts: imx8mp: add HSIO power-domains
This adds the GPC and HSIO blk-ctrl nodes providing power control for the high-speed (USB and PCIe) IOs. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
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@ -523,6 +523,21 @@
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#address-cells = <1>;
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#size-cells = <0>;
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pgc_pcie_phy: power-domain@1 {
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#power-domain-cells = <0>;
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reg = <IMX8MP_POWER_DOMAIN_PCIE_PHY>;
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};
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pgc_usb1_phy: power-domain@2 {
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#power-domain-cells = <0>;
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reg = <IMX8MP_POWER_DOMAIN_USB1_PHY>;
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};
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pgc_usb2_phy: power-domain@3 {
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#power-domain-cells = <0>;
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reg = <IMX8MP_POWER_DOMAIN_USB2_PHY>;
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};
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pgc_gpu2d: power-domain@6 {
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#power-domain-cells = <0>;
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reg = <IMX8MP_POWER_DOMAIN_GPU2D>;
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@ -549,6 +564,16 @@
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<&clk IMX8MP_CLK_GPU3D_SHADER_CORE>;
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power-domains = <&pgc_gpumix>;
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};
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pgc_hsiomix: power-domains@17 {
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#power-domain-cells = <0>;
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reg = <IMX8MP_POWER_DOMAIN_HSIOMIX>;
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clocks = <&clk IMX8MP_CLK_HSIO_AXI>,
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<&clk IMX8MP_CLK_HSIO_ROOT>;
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assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
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assigned-clock-rates = <500000000>;
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};
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};
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};
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};
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@ -970,6 +995,28 @@
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};
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};
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aips4: bus@32c00000 {
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compatible = "fsl,aips-bus", "simple-bus";
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reg = <0x32c00000 0x400000>;
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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hsio_blk_ctrl: blk-ctrl@32f10000 {
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compatible = "fsl,imx8mp-hsio-blk-ctrl", "syscon";
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reg = <0x32f10000 0x24>;
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clocks = <&clk IMX8MP_CLK_USB_ROOT>,
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<&clk IMX8MP_CLK_PCIE_ROOT>;
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clock-names = "usb", "pcie";
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power-domains = <&pgc_hsiomix>, <&pgc_hsiomix>,
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<&pgc_usb1_phy>, <&pgc_usb2_phy>,
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<&pgc_hsiomix>, <&pgc_pcie_phy>;
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power-domain-names = "bus", "usb", "usb-phy1",
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"usb-phy2", "pcie", "pcie-phy";
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#power-domain-cells = <1>;
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};
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};
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gpu3d: gpu@38000000 {
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compatible = "vivante,gc";
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reg = <0x38000000 0x8000>;
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@ -1030,6 +1077,7 @@
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clock-names = "phy";
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assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
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assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
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power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY1>;
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#phy-cells = <0>;
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status = "disabled";
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};
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@ -1042,6 +1090,7 @@
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<&clk IMX8MP_CLK_USB_ROOT>;
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clock-names = "hsio", "suspend";
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interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
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#address-cells = <1>;
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#size-cells = <1>;
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dma-ranges = <0x40000000 0x40000000 0xc0000000>;
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@ -1055,9 +1104,6 @@
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<&clk IMX8MP_CLK_USB_CORE_REF>,
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<&clk IMX8MP_CLK_USB_ROOT>;
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clock-names = "bus_early", "ref", "suspend";
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assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
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assigned-clock-rates = <500000000>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&usb3_phy0>, <&usb3_phy0>;
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phy-names = "usb2-phy", "usb3-phy";
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@ -1073,6 +1119,7 @@
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clock-names = "phy";
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assigned-clocks = <&clk IMX8MP_CLK_USB_PHY_REF>;
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assigned-clock-parents = <&clk IMX8MP_CLK_24M>;
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power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB_PHY2>;
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#phy-cells = <0>;
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status = "disabled";
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};
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@ -1085,6 +1132,7 @@
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<&clk IMX8MP_CLK_USB_ROOT>;
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clock-names = "hsio", "suspend";
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interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&hsio_blk_ctrl IMX8MP_HSIOBLK_PD_USB>;
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#address-cells = <1>;
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#size-cells = <1>;
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dma-ranges = <0x40000000 0x40000000 0xc0000000>;
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@ -1098,9 +1146,6 @@
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<&clk IMX8MP_CLK_USB_CORE_REF>,
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<&clk IMX8MP_CLK_USB_ROOT>;
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clock-names = "bus_early", "ref", "suspend";
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assigned-clocks = <&clk IMX8MP_CLK_HSIO_AXI>;
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assigned-clock-parents = <&clk IMX8MP_SYS_PLL2_500M>;
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assigned-clock-rates = <500000000>;
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interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
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phys = <&usb3_phy1>, <&usb3_phy1>;
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phy-names = "usb2-phy", "usb3-phy";
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