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net: phy: add qca8081 config_init

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Add the qca8081 phy driver config_init function, which includes:
1. Enable fast restrain.
2. Add 802.3az configurations.
3. Initialize ADC threshold as 100mv.

Signed-off-by: Luo Jie <luoj@codeaurora.org>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Luo Jie 2021-10-24 16:27:35 +08:00 committed by David S. Miller
parent 63c67f526d
commit 2acdd43fe0
1 changed files with 107 additions and 0 deletions
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107
drivers/net/phy/at803x.c
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@ -178,6 +178,51 @@
#define AT803X_KEEP_PLL_ENABLED BIT(0)
#define AT803X_DISABLE_SMARTEEE BIT(1)
/* ADC threshold */
#define QCA808X_PHY_DEBUG_ADC_THRESHOLD 0x2c80
#define QCA808X_ADC_THRESHOLD_MASK GENMASK(7, 0)
#define QCA808X_ADC_THRESHOLD_80MV 0
#define QCA808X_ADC_THRESHOLD_100MV 0xf0
#define QCA808X_ADC_THRESHOLD_200MV 0x0f
#define QCA808X_ADC_THRESHOLD_300MV 0xff
/* CLD control */
#define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7 0x8007
#define QCA808X_8023AZ_AFE_CTRL_MASK GENMASK(8, 4)
#define QCA808X_8023AZ_AFE_EN 0x90
/* AZ control */
#define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL 0x8008
#define QCA808X_MMD3_AZ_TRAINING_VAL 0x1c32
#define QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB 0x8014
#define QCA808X_MSE_THRESHOLD_20DB_VALUE 0x529
#define QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB 0x800E
#define QCA808X_MSE_THRESHOLD_17DB_VALUE 0x341
#define QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB 0x801E
#define QCA808X_MSE_THRESHOLD_27DB_VALUE 0x419
#define QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB 0x8020
#define QCA808X_MSE_THRESHOLD_28DB_VALUE 0x341
#define QCA808X_PHY_MMD7_TOP_OPTION1 0x901c
#define QCA808X_TOP_OPTION1_DATA 0x0
#define QCA808X_PHY_MMD3_DEBUG_1 0xa100
#define QCA808X_MMD3_DEBUG_1_VALUE 0x9203
#define QCA808X_PHY_MMD3_DEBUG_2 0xa101
#define QCA808X_MMD3_DEBUG_2_VALUE 0x48ad
#define QCA808X_PHY_MMD3_DEBUG_3 0xa103
#define QCA808X_MMD3_DEBUG_3_VALUE 0x1698
#define QCA808X_PHY_MMD3_DEBUG_4 0xa105
#define QCA808X_MMD3_DEBUG_4_VALUE 0x8001
#define QCA808X_PHY_MMD3_DEBUG_5 0xa106
#define QCA808X_MMD3_DEBUG_5_VALUE 0x1111
#define QCA808X_PHY_MMD3_DEBUG_6 0xa011
#define QCA808X_MMD3_DEBUG_6_VALUE 0x5f85
MODULE_DESCRIPTION("Qualcomm Atheros AR803x and QCA808X PHY driver");
MODULE_AUTHOR("Matus Ujhelyi");
MODULE_LICENSE("GPL");
@ -1489,6 +1534,67 @@ static int qca83xx_suspend(struct phy_device *phydev)
return 0;
}
static int qca808x_phy_fast_retrain_config(struct phy_device *phydev)
{
int ret;
/* Enable fast retrain */
ret = genphy_c45_fast_retrain(phydev, true);
if (ret)
return ret;
phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1,
QCA808X_TOP_OPTION1_DATA);
phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB,
QCA808X_MSE_THRESHOLD_20DB_VALUE);
phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB,
QCA808X_MSE_THRESHOLD_17DB_VALUE);
phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB,
QCA808X_MSE_THRESHOLD_27DB_VALUE);
phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB,
QCA808X_MSE_THRESHOLD_28DB_VALUE);
phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1,
QCA808X_MMD3_DEBUG_1_VALUE);
phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4,
QCA808X_MMD3_DEBUG_4_VALUE);
phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5,
QCA808X_MMD3_DEBUG_5_VALUE);
phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3,
QCA808X_MMD3_DEBUG_3_VALUE);
phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6,
QCA808X_MMD3_DEBUG_6_VALUE);
phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_2,
QCA808X_MMD3_DEBUG_2_VALUE);
return 0;
}
static int qca808x_config_init(struct phy_device *phydev)
{
int ret;
/* Active adc&vga on 802.3az for the link 1000M and 100M */
ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7,
QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN);
if (ret)
return ret;
/* Adjust the threshold on 802.3az for the link 1000M */
ret = phy_write_mmd(phydev, MDIO_MMD_PCS,
QCA808X_PHY_MMD3_AZ_TRAINING_CTRL, QCA808X_MMD3_AZ_TRAINING_VAL);
if (ret)
return ret;
/* Config the fast retrain for the link 2500M */
ret = qca808x_phy_fast_retrain_config(phydev);
if (ret)
return ret;
/* Configure adc threshold as 100mv for the link 10M */
return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD,
QCA808X_ADC_THRESHOLD_MASK, QCA808X_ADC_THRESHOLD_100MV);
}
static int qca808x_read_status(struct phy_device *phydev)
{
int ret;
@ -1690,6 +1796,7 @@ static struct phy_driver at803x_driver[] = {
.suspend = genphy_suspend,
.resume = genphy_resume,
.read_status = qca808x_read_status,
.config_init = qca808x_config_init,
}, };
module_phy_driver(at803x_driver);