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irqchip/gic: Atomically update affinity
commit005c34ae4b
upstream. The GIC driver uses a RMW sequence to update the affinity, and relies on the gic_lock_irqsave/gic_unlock_irqrestore sequences to update it atomically. But these sequences only expand into anything meaningful if the BL_SWITCHER option is selected, which almost never happens. It also turns out that using a RMW and locks is just as silly, as the GIC distributor supports byte accesses for the GICD_TARGETRn registers, which when used make the update atomic by definition. Drop the terminally broken code and replace it by a byte write. Fixes:04c8b0f82c
("irqchip/gic: Make locking a BL_SWITCHER only feature") Cc: stable@vger.kernel.org Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -329,10 +329,8 @@ static int gic_irq_set_vcpu_affinity(struct irq_data *d, void *vcpu)
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static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
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bool force)
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{
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void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + (gic_irq(d) & ~3);
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unsigned int cpu, shift = (gic_irq(d) % 4) * 8;
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u32 val, mask, bit;
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unsigned long flags;
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void __iomem *reg = gic_dist_base(d) + GIC_DIST_TARGET + gic_irq(d);
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unsigned int cpu;
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if (!force)
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cpu = cpumask_any_and(mask_val, cpu_online_mask);
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@ -342,13 +340,7 @@ static int gic_set_affinity(struct irq_data *d, const struct cpumask *mask_val,
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if (cpu >= NR_GIC_CPU_IF || cpu >= nr_cpu_ids)
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return -EINVAL;
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gic_lock_irqsave(flags);
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mask = 0xff << shift;
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bit = gic_cpu_map[cpu] << shift;
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val = readl_relaxed(reg) & ~mask;
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writel_relaxed(val | bit, reg);
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gic_unlock_irqrestore(flags);
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writeb_relaxed(gic_cpu_map[cpu], reg);
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irq_data_update_effective_affinity(d, cpumask_of(cpu));
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return IRQ_SET_MASK_OK_DONE;
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