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cxl: Workaround XSL bug that does not clear the RA bit after a reset

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An issue was noted in our debug logs where the XSL would leave the RA
bit asserted after an AFU reset operation, which would effectively
prevent further AFU reset operations from working.

Workaround the issue by clearing the RA bit with an MMIO write if it is
still asserted after any AFU control operation.

Signed-off-by: Ian Munsie <imunsie@au1.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Ian Munsie 2016-06-30 04:51:26 +10:00 committed by Michael Ellerman
parent 5e7823c9bc
commit 2a4f667aad
1 changed files with 10 additions and 0 deletions
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10
drivers/misc/cxl/native.c
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@ -55,6 +55,16 @@ static int afu_control(struct cxl_afu *afu, u64 command, u64 clear,
cpu_relax();
AFU_Cntl = cxl_p2n_read(afu, CXL_AFU_Cntl_An);
};
if (AFU_Cntl & CXL_AFU_Cntl_An_RA) {
/*
* Workaround for a bug in the XSL used in the Mellanox CX4
* that fails to clear the RA bit after an AFU reset,
* preventing subsequent AFU resets from working.
*/
cxl_p2n_write(afu, CXL_AFU_Cntl_An, AFU_Cntl & ~CXL_AFU_Cntl_An_RA);
}
pr_devel("AFU command complete: %llx\n", command);
afu->enabled = enabled;
out: