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platform/x86: intel_pmc_core: Include Reserved IP for LTR
Recently introduced commit "platform/x86: intel_pmc_core: Show Latency Tolerance info <51337cd94d18184601ac0fb4cf1a02b8bbabc3d7> skipped the LTR from a reserved IP. Though this doesn't cause any functional issue but it is needed for the consumers of "ltr_ignore" as the index printing for "ltr_show" is missing. For example, w/o this change, a user that wants to ignore LTR from ME would do something like echo 5 > ltr_ignore but the index for ME is 6. Printing a reserved IP helps to properly calculate LTR ignore offsets. Cc: "David E. Box" <david.e.box@intel.com> Cc: Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@linux.intel.com> Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
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@ -108,6 +108,7 @@ static const struct pmc_bit_map spt_ltr_show_map[] = {
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{"SATA", SPT_PMC_LTR_SATA},
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{"GIGABIT_ETHERNET", SPT_PMC_LTR_GBE},
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{"XHCI", SPT_PMC_LTR_XHCI},
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{"Reserved", SPT_PMC_LTR_RESERVED},
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{"ME", SPT_PMC_LTR_ME},
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/* EVA is Enterprise Value Add, doesn't really exist on PCH */
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{"EVA", SPT_PMC_LTR_EVA},
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@ -276,6 +277,7 @@ static const struct pmc_bit_map cnp_ltr_show_map[] = {
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{"SATA", CNP_PMC_LTR_SATA},
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{"GIGABIT_ETHERNET", CNP_PMC_LTR_GBE},
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{"XHCI", CNP_PMC_LTR_XHCI},
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{"Reserved", CNP_PMC_LTR_RESERVED},
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{"ME", CNP_PMC_LTR_ME},
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/* EVA is Enterprise Value Add, doesn't really exist on PCH */
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{"EVA", CNP_PMC_LTR_EVA},
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@ -46,6 +46,7 @@
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#define SPT_PMC_LTR_SATA 0x368
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#define SPT_PMC_LTR_GBE 0x36C
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#define SPT_PMC_LTR_XHCI 0x370
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#define SPT_PMC_LTR_RESERVED 0x374
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#define SPT_PMC_LTR_ME 0x378
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#define SPT_PMC_LTR_EVA 0x37C
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#define SPT_PMC_LTR_SPC 0x380
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@ -156,6 +157,7 @@ enum ppfear_regs {
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#define CNP_PMC_LTR_SATA 0x1B68
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#define CNP_PMC_LTR_GBE 0x1B6C
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#define CNP_PMC_LTR_XHCI 0x1B70
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#define CNP_PMC_LTR_RESERVED 0x1B74
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#define CNP_PMC_LTR_ME 0x1B78
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#define CNP_PMC_LTR_EVA 0x1B7C
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#define CNP_PMC_LTR_SPC 0x1B80
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