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arm64: cpufeature: List early Cortex-A510 parts as having broken dbm
Versions of Cortex-A510 before r0p3 are affected by a hardware erratum where the hardware update of the dirty bit is not correctly ordered. Add these cpus to the cpu_has_broken_dbm list. Signed-off-by: James Morse <james.morse@arm.com> Link: https://lore.kernel.org/r/20220125154040.549272-3-james.morse@arm.com Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
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@ -98,6 +98,8 @@ stable kernels.
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A77 | #1508412 | ARM64_ERRATUM_1508412 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A510 | #2051678 | ARM64_ERRATUM_2051678 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A710 | #2119858 | ARM64_ERRATUM_2119858 |
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+----------------+-----------------+-----------------+-----------------------------+
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| ARM | Cortex-A710 | #2054223 | ARM64_ERRATUM_2054223 |
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@ -670,6 +670,16 @@ config ARM64_ERRATUM_1508412
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config ARM64_WORKAROUND_TRBE_OVERWRITE_FILL_MODE
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bool
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config ARM64_ERRATUM_2051678
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bool "Cortex-A510: 2051678: disable Hardware Update of the page table dirty bit"
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help
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This options adds the workaround for ARM Cortex-A510 erratum ARM64_ERRATUM_2051678.
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Affected Coretex-A510 might not respect the ordering rules for
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hardware update of the page table's dirty bit. The workaround
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is to not enable the feature on affected CPUs.
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If unsure, say Y.
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config ARM64_ERRATUM_2119858
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bool "Cortex-A710/X2: 2119858: workaround TRBE overwriting trace data in FILL mode"
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default y
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@ -1645,6 +1645,9 @@ static bool cpu_has_broken_dbm(void)
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MIDR_ALL_VERSIONS(MIDR_CORTEX_A55),
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/* Kryo4xx Silver (rdpe => r1p0) */
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MIDR_REV(MIDR_QCOM_KRYO_4XX_SILVER, 0xd, 0xe),
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#endif
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#ifdef CONFIG_ARM64_ERRATUM_2051678
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MIDR_REV_RANGE(MIDR_CORTEX_A510, 0, 0, 2),
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#endif
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{},
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};
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