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- Probe whether hardware error injection (direct MSR writes) is possible

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when injecting errors on AMD platforms. In some cases, the platform
 could prohibit those.
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Merge tag 'ras_core_for_v6.0_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip

Pull RAS update from Borislav Petkov:
 "A single RAS change:

   - Probe whether hardware error injection (direct MSR writes) is
     possible when injecting errors on AMD platforms. In some cases, the
     platform could prohibit those"

* tag 'ras_core_for_v6.0_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  x86/mce: Check whether writes to MCA_STATUS are getting ignored
This commit is contained in:
Linus Torvalds 2022-08-01 09:29:41 -07:00
commit 296d3b3e05
2 changed files with 48 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

47
arch/x86/kernel/cpu/mce/inject.c
View File

@ -33,6 +33,8 @@
#include "internal.h"
static bool hw_injection_possible = true;
/*
* Collect all the MCi_XXX settings
*/
@ -339,6 +341,8 @@ static int __set_inj(const char *buf)
for (i = 0; i < N_INJ_TYPES; i++) {
if (!strncmp(flags_options[i], buf, strlen(flags_options[i]))) {
if (i > SW_INJ && !hw_injection_possible)
continue;
inj_type = i;
return 0;
}
@ -717,11 +721,54 @@ static void __init debugfs_init(void)
&i_mce, dfs_fls[i].fops);
}
static void check_hw_inj_possible(void)
{
int cpu;
u8 bank;
/*
* This behavior exists only on SMCA systems though its not directly
* related to SMCA.
*/
if (!cpu_feature_enabled(X86_FEATURE_SMCA))
return;
cpu = get_cpu();
for (bank = 0; bank < MAX_NR_BANKS; ++bank) {
u64 status = MCI_STATUS_VAL, ipid;
/* Check whether bank is populated */
rdmsrl(MSR_AMD64_SMCA_MCx_IPID(bank), ipid);
if (!ipid)
continue;
toggle_hw_mce_inject(cpu, true);
wrmsrl_safe(mca_msr_reg(bank, MCA_STATUS), status);
rdmsrl_safe(mca_msr_reg(bank, MCA_STATUS), &status);
if (!status) {
hw_injection_possible = false;
pr_warn("Platform does not allow *hardware* error injection."
"Try using APEI EINJ instead.\n");
}
toggle_hw_mce_inject(cpu, false);
break;
}
put_cpu();
}
static int __init inject_init(void)
{
if (!alloc_cpumask_var(&mce_inject_cpumask, GFP_KERNEL))
return -ENOMEM;
check_hw_inj_possible();
debugfs_init();
register_nmi_handler(NMI_LOCAL, mce_raise_notify, 0, "mce_notify");

2
arch/x86/kernel/cpu/mce/internal.h
View File

@ -211,7 +211,7 @@ noinstr u64 mce_rdmsrl(u32 msr);
static __always_inline u32 mca_msr_reg(int bank, enum mca_msr reg)
{
if (mce_flags.smca) {
if (cpu_feature_enabled(X86_FEATURE_SMCA)) {
switch (reg) {
case MCA_CTL: return MSR_AMD64_SMCA_MCx_CTL(bank);
case MCA_ADDR: return MSR_AMD64_SMCA_MCx_ADDR(bank);